參數(shù)資料
型號: XRT86VL32IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 54/174頁
文件大小: 903K
代理商: XRT86VL32IB
XRT86VL32
49
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
30: PRBS C
ONTROL
A
ND
S
TATUS
R
EGISTER
0 (PRBSCSR0) H
EX
A
DDRESS
: 0
XN
121
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
3
PRBS_Switch
R/W
0
PRBS Switch
This bit enables or disables the PRBS switch function within the
XRT86VL32 device.
By enabling the PRBS switch function, PRBS functionality will be
switched between the receive and transmit framer. E1 Receive
framer will generate the PRBS pattern and insert it onto the receive
backplane interface, and E1 Transmit Framer will be monitoring the
transmit backplane interface for PRBS pattern and declare PRBS
LOCK if PRBS has locked onto the input pattern.
If PRBS switch is disabled, E1 Transmit framer will generate the
PRBS pattern to the line interface and the receive framer will be
monitoring the line for PRBS/QRTS pattern and declare PRBS
LOCK if PRBS has locked onto the input pattern.
0 = Disables the PRBS Switch Feature.
1 = Enables the PRBS Switch Feature.
2
BER[1]
R/W
0
Bit Error Rate
This bit is used to insert PRBS bit error at the rates presented at the
table below. The exact function of this bit depends on whether
PRBS switch function is enabled or not. (bit 3 within this register).
If the PRBS switch function is disabled, bit error will be inserted by
the E1 transmit framer out to the line interface if this bit is enabled.
If the PRBS switch function is enabled, bit error will be inserted by
the E1 receive framer out to the receive backplane interface if this
bit is enabled.
1
BER[0]
R/W
0
BER[1:0]
BIT ERROR RATE
00
Disable Bit Error insertion to the transmit output
or receive backplane interface
01
Bit Error is inserted to the transmit output or
receive backplane interface at a rate of 1/1000
(one out of one Thousand)
10
Bit Error is inserted to the transmit output or
receive backplane interface at a rate of 1/
1,000,000 (one out of one million)
11
Disable Bit Error insertion to the transmit output
or receive backplane interface
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