參數(shù)資料
型號: XRT86VL32IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 96/174頁
文件大?。?/td> 903K
代理商: XRT86VL32IB
XRT86VL32
91
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
73: PMON R
ECEIVE
L
INE
C
ODE
V
IOLATION
C
OUNTER
MSB (RLCVCU) H
EX
A
DDRESS
: 0
X
n900
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
RLCVC[15]
RUR
0
Performance Monitor “Receive Line Code Violation” 16-Bit
Counter - Upper Byte:
These RESET-upon-READ bits, along with that within the PMON
Receive Line Code Violation Counter Register LSB combine to
reflect the cumulative number of instances that Line Code Violation
has been detected by the Receive E1 Framer block since the last
read of this register.
This register contains the Most Significant byte of this 16-bit of the
Line Code Violation counter.
N
OTE
:
For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
RLCVC[14]
RUR
0
5
RLCVC[13]
RUR
0
4
RLCVC[12]
RUR
0
3
RLCVC[11]
RUR
0
2
RLCVC[10]
RUR
0
1
RLCVC[9]
RUR
0
0
RLCVC[8]
RUR
0
T
ABLE
74: PMON R
ECEIVE
L
INE
C
ODE
V
IOLATION
C
OUNTER
LSB (RLCVCL) H
EX
A
DDRESS
: 0
X
n901
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
RLCVC[7]
RUR
0
Performance Monitor “Receive Line Code Violation” 16-Bit
Counter - Lower Byte:
These RESET-upon-READ bits, along with that within the PMON
Receive Line Code Violation Counter Register MSB combine to
reflect the cumulative number of instances that Line Code Violation
has been detected by the Receive E1 Framer block since the last
read of this register.
This register contains the Least Significant byte of this 16-bit of the
Line Code Violation counter.
N
OTE
:
For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
RLCVC[6]
RUR
0
5
RLCVC[5]
RUR
0
4
RLCVC[4]
RUR
0
3
RLCVC[3]
RUR
0
2
RLCVC[2]
RUR
0
1
RLCVC[1]
RUR
0
0
RLCVC[0]
RUR
0
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