XRT86VL32
93
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
77: PMON R
ECEIVE
S
EVERELY
E
RRORED
F
RAME
C
OUNTER
(RSEFC) H
EX
A
DDRESS
: 0
X
n904
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
RSEFC[7]
RUR
0
Performance Monitor - Receive Severely Errored frame Counter
(8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Receive Severely Errored Frames have been
detected by the E1 Framer since the last read of this register.
Severely Errored Frame is defined as the occurrence of two consec-
utive errored frame alignment signals without causing loss of frame
condition.
6
RSEFC[6]
RUR
0
5
RSEFC[5]
RUR
0
4
RSEFC[4]
RUR
0
3
RSEFC[3]
RUR
0
2
RSEFC[2]
RUR
0
1
RSEFC[1]
RUR
0
0
RSEFC[0]
RUR
0
T
ABLE
78: PMON R
ECEIVE
CRC-4 B
IT
E
RROR
C
OUNTER
- MSB (RSBBECU) H
EX
A
DDRESS
: 0
X
n905
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
RSBBEC[15]
RUR
0
Performance Monitor “Receive Synchronization Bit Error 16-Bit
Counter” - Upper Byte:
These RESET-upon-READ bits, along with that within the “PMON
Receive Synchronization Bit Error Counter Register LSB” combine
to reflect the cumulative number of instances that the Receive Syn-
chronization Bit errors has been detected by the Receive E1 Framer
block since the last read of this register.
This register contains the Most Significant byte of this 16-bit of the
Receive Synchronization Bit Error counter.
N
OTE
:
For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
RSBBEC[14]
RUR
0
5
RSBBEC[13]
RUR
0
4
RSBBEC[12]
RUR
0
3
RSBBEC[11]
RUR
0
2
RSBBEC[10]
RUR
0
1
RSBBEC[9]
RUR
0
0
RSBBEC[8]
RUR
0
T
ABLE
79: PMON R
ECEIVE
CRC-4 B
LOCK
E
RROR
C
OUNTER
- LSB (RSBBECL) H
EX
A
DDRESS
: 0
X
n906
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
RSBBEC[7]
RUR
0
Performance Monitor “Receive Synchronization Bit Error 16-Bit
Counter” - Lower Byte:
These RESET-upon-READ bits, along with that within the “PMON
Receive Synchronization Bit Error Counter Register MSB” combine
to reflect the cumulative number of instances that the Receive Syn-
chronization Bit errors has been detected by the Receive E1 Framer
block since the last read of this register.
This register contains the Least Significant byte of this 16-bit of the
Receive Synchronization Bit Error counter.
N
OTE
:
For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
RSBBEC[6]
RUR
0
5
RSBBEC[5]
RUR
0
4
RSBBEC[4]
RUR
0
3
RSBBEC[3]
RUR
0
2
RSBBEC[2]
RUR
0
1
RSBBEC[1]
RUR
0
0
RSBBEC[0]
RUR
0