參數(shù)資料
型號: XRT86VL32IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 165/174頁
文件大小: 903K
代理商: XRT86VL32IB
XRT86VL32
160
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
126: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
3 (LIUCCAR3) H
EX
A
DDRESS
: 0
X
0F
N
A
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
R/W
0
6-0
Arb_seg3
R/W
0
Arbitrary Transmit Pulse Shape, Segment 3
These seven bits form the third of the eight segments of the transmit
shape pulse when the XRT86VL32 is configured in “Arbitrary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
N
OTE
:
Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
T
ABLE
127: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
4 (LIUCCAR4) H
EX
A
DDRESS
: 0
X
0F
N
B
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
R/W
0
6-0
Arb_seg4
R/W
0
Arbitrary Transmit Pulse Shape, Segment 4
These seven bits form the forth of the eight segments of the transmit
shape pulse when the XRT86VL32 is configured in “Arbitrary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
Arbitrary mode is enabled by writing to the EQC[4:0] bits in register
0x0Fn0.
T
ABLE
128: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
5 (LIUCCAR5) H
EX
A
DDRESS
: 0
X
0F
N
C
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
R/W
0
6-0
Arb_seg5
R/W
0
Arbitrary Transmit Pulse Shape, Segment 5
These seven bits form the fifth of the eight segments of the transmit
shape pulse when the XRT86VL32 is configured in “Arbitrary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
Arbitrary mode is enabled by writing to the EQC[4:0] bits in register
0x0Fn0.
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