參數(shù)資料
型號: XRT86VL32IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 32/174頁
文件大?。?/td> 903K
代理商: XRT86VL32IB
XRT86VL32
27
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
9: R
ECEIVE
S
IGNALING
& D
ATA
L
INK
S
ELECT
R
EGISTER
(RSDLSR) H
EX
A
DDRESS
: 0
X
n10C
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
RxSa8ENB
R/W
0
Receive Sa8 Enable
This bit is used to specify whether or not Sa 8 (bit 7 within timeslot 0 of non-FAS
frames) will be used to receive data link information
0 = Sa8 is not used to receive data link information
1 = Sa8 is used to receive data link information
N
OTE
:
This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The
National bits have been configured to receive data link bits).
6
RxSa7ENB
R/W
0
Receive Sa7 Enable
This bit is used to specify whether or not Sa 7 (bit 6 within timeslot 0 of non-FAS
frames) will be used to receive data link information
0 = Sa7 is not used to receive data link information
1 = Sa7 is used to receive data link information
N
OTE
:
This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The
National bits have been configured to receive data link bits).
5
RxSa6ENB
R/W
0
Receive Sa6 Enable
This bit is used to specify whether or not Sa 6 (bit 5 within timeslot 0 of non-FAS
frames) will be used to receive data link information
0 = Sa6 is not used to receive data link information
1 = Sa6 is used to receive data link information
N
OTE
:
This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The
National bits have been configured to receive data link bits).
4
RxSa5ENB
R/W
0
Receive Sa5 Enable
This bit is used to specify whether or not Sa 5 (bit 4 within timeslot 0 of non-FAS
frames) will be used to receive data link information
0 = Sa5 is not used to receive data link information
1 = Sa5 is used to receive data link information
N
OTE
:
This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The
National bits have been configured to receive data link bits).
3
RxSa4ENB
R/W
0
Receive Sa4 Enable
This bit is used to specify whether or not Sa 4 (bit 3 within timeslot 0 of non-FAS
frames) will be used to receive data link information
0 = Sa4 is not used to receive data link information
1 = Sa4 is used to receive data link information
N
OTE
:
This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The
National bits have been configured to receive data link bits).
相關PDF資料
PDF描述
XRT86VL34_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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相關代理商/技術參數(shù)
參數(shù)描述
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XRT86VL34 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL34_07 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL34_1 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL34_2 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION