參數(shù)資料
型號: XRT86VL32IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 52/174頁
文件大?。?/td> 903K
代理商: XRT86VL32IB
XRT86VL32
47
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
1
TxIMODE[1]
R/W
0
Transmit Interface Mode selection
This bit determines the transmit interface speed. The exact function of
these two bits depends on whether Multiplexed mode is enabled or dis-
abled. Table 28 and Table 29shows the functions of these bits for non-
multiplexed and multiplexed modes.:
0
TxIMODE[0]
R/W
0
T
ABLE
27: T
RANSMIT
I
NTERFACE
C
ONTROL
R
EGISTER
(TICR) H
EX
A
DDRESS
:0
X
n120
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
T
ABLE
28: T
RANSMIT
I
NTERFACE
S
PEED
W
HEN
M
ULTIPLEXED
M
ODE
IS
D
ISABLED
(T
X
MUXEN = 0)
T
X
IMODE[1:0]
T
RANSMIT
I
NTERFACE
S
PEED
00
2.048Mbit/s. (Base Rate)
Transmit Backplane interface signals include:
TxSERCLK is an input or output clock at
2.048MHz
TxMSYNC is the superframe boundary at 2ms
TxSYNC is the single frame boundary at 125 us
TxSER is the base-rate data input
01
2.048Mbit/ (High-speed MVIP Mode)
Transmit Backplane interface signals include:
TxSERCLK is an input clock at 2.048MHz
TxMSYNC will become the high speed input clock
at 2.048MHz to input high-speed data
TxSYNC indicates the single frame boundary
TxSER is the high-speed data input
10
4.096Mbit/s High-speed mode:
Transmit Backplane interface signals include:
TxSERCLK is an input clock at 2.048MHz
TxMSYNC will become the high speed input clock
at 4.096MHz to input high-speed data
TxSYNC indicates the single frame boundary
TxSER is the high-speed data input
11
8.192Mbit/s High-speed mode:
Transmit Backplane interface signals include:
TxSERCLK is an input clock at 2.048MHz
TxMSYNC will become the high speed input clock
at 8.192MHz to input high-speed data
TxSYNC indicates the single frame boundary
TxSER is the high-speed data input
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