參數(shù)資料
型號: XRT86VL32IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 20/174頁
文件大小: 903K
代理商: XRT86VL32IB
XRT86VL32
15
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
3-2
CRC MF Align
Sel[1:0]
R/W
00
CRC Multiframe Alignment Declaration Criteria Select [1:0]
These two bits allow the user to select which CRC-Multiframe Alignment
Declaration criteria the Receive E1 Framer block will employ. The Receive
E1 Framer block will check for CRC Multiframe Alignment by checking the
incoming E1 data-stream and determining whether the international bits (bit
1 of timeslot 0) of non-FAS frames match the CRC multiframe alignment
pattern (0,0,1,0,1,1,E1,E2). The table below provides more details on the
three different CRC Multiframe Alignment Declaration Criteria.
N
OTE
:
For information on the criteria that the Receive E1 Framer block
uses to declare the “Loss of CRC Multiframe Alignment” defect
condition, please see register description for the Framing Control
Register (FCR - 0xn10B)
1
Additional Frame
Check Enable -
FAS
R/W
0
Additional Frame Check Enable - FAS Frame Alignment Declaration
This bit permits the user to configure the Receive E1 Framer block to per-
form some “additional FAS frame synchronization checking” prior to declar-
ing “FAS Frame Alignment”. If the user implements this feature, then the
Receive E1 Framer block will perform some more testing on two additional
E1 frames, prior to declaring the “FAS Frame Alignment” condition.
0 - Disables this additional FAS frame checking.
1 - Enables this additional FAS frame checking.
T
ABLE
4: F
RAMING
S
ELECT
R
EGISTER
(FSR) H
EX
A
DDRESS
: 0
X
n107
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
CRC MF
A
LIGN
S
EL
[1:0]
CRC M
ULTIFRAME
A
LIGNMENT
D
ECLARATION
C
RITERIA
S
ELECTED
00
CRC Multiframe Alignment is Disabled
01
CRC Multiframe Alignment is Enabled. Alignment is
declared if at least 1 valid CRC multiframe alignment
signal (0,0,1,0,1,1,E1,E2) is observed within 8ms.
10
CRC Multiframe Alignment is Enabled. Alignment is
declared if at least 2 valid CRC multiframe alignment
signals (0,0,1,0,1,1,E1,E2) are observed within 8ms.
11
CRC Multiframe Alignment is Enabled. Alignment is
declared if at least 3 valid CRC multiframe alignment
signals (0,0,1,0,1,1,E1,E2) are observed within 8ms.
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