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| 型號： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁數(shù)： | 28/98頁 |
| 文件大小： | 1365K |
| 代理商： | 23913A |
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16
Model-Specific Registers Overview
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Standard Model-Specific Registers (All Models)
This section describes the four standard MSRs that every model
and stepping of the AMD-K6 family of processors support
identically. See the appropriate AMD-K6 or AMD-K6E
processor data sheet for more detail on these standard
registers.
Machine-Check
Address Register
(MCAR) and
Machine-Check Type
Register (MCTR)
The processor does not support the generation of a machine
check exception, but does provide a 64-bit Machine Check
Address Register (MCAR) and a 64-bit Machine Check Type
Register (MCTR) for software compatibility. Because the
processor does not support machine check exceptions, the
contents of the MCAR and MCTR are only affected by the
WRMSR instruction and by RESET being sampled asserted
(where all bits in each register are reset to 0).
The processor also provides the Machine Check Exception
(MCE) bit in Control Register 4 (CR4, bit 6) as a read-write bit.
However, the state of this bit has no effect on the operation of
the processor.
Test Register 12
(TR12)
The processor provides the 64-bit Test Register 12 (TR12), but
only the Cache Inhibit (CI) bit (bit 3 of TR12) is supported. All
other bits in TR12 have no effect on the processor’s operation.
Note:
The I/O Trap Restart function (bit 9 of TR12) is always
enabled on AMD-K6 processors.
Time Stamp Counter
(TSC)
With each processor clock cycle, the processor increments a
64-bit time stamp counter (TSC) MSR. The counter can be
written or read using the WRMSR or RDMSR instructions when
the ECX register contains the value 10h and current privilege
level (CPL) = 0. The counter can also be read using the RDTSC
instruction, but the required privilege level for this instruction
is determined by the Time Stamp Disable (TSD) bit in CR4.
With either of these instructions, the EDX and EAX registers
hold the upper and lower dwords of the 64-bit value to be
written to or read from the TSC, as follows:
EDX—Upper 32 bits of TSC
EAX—Lower 32 bits of TSC
I
I
The TSC can be loaded with any arbitrary value. This feature is
compatible with the Pentium processor.
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