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| 型號(hào)： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁(yè)數(shù)： | 43/98頁(yè) |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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Model 8/[F:8] Registers
31
23913A/0—November 2000
Embedded AMD-K6 Processors BIOS Design Guide
Preliminary Information
Figure 7.
UC/WC Cacheability Control Register (UWCCR)
(Models 8/[F:8], 9, and D)
Physical Base
Address n (n=0, 1)
This address is the 15 most-significant bits of the physical base
address of the memory range. The least-significant 17 bits of the
base address are not needed because the base address is by
definition always aligned on a 128-Kbyte boundary.
Physical Address
Mask n (n=0, 1)
This value is the 15 most-significant bits of a physical address
mask that is used to define the size of the memory range. This
mask is logically ANDed with both the physical base address
field of the UWCCR register and the physical address
generated by the processor. If the results of the two AND
operations are equal, then the generated physical address is
considered within the range. That is, if:
Mask & Physical Base Address = Mask & Physical Address Generated
then, the physical address generated by the processor is in the
range.
WCn (n=0, 1)
When set to 1, this memory range is defined as write-
combinable (refer to Table 15). Write-combinable memory is
uncacheable.
UCn (n=0, 1)
When set to 1, this memory range is defined as uncacheable
(refer to Table 15).
Table 15. WC/UC Memory Type for UWCCR Register
16
0
63
Physical Address Mask 0
17
31
Physical Base Address 0
1
2
Physical Address Mask 1
Physical Base Address 1
32
33
34
48
49
U
C
0
W
C
0
U
C
1
W
C
1
MTRR1
MTRR0
Symbol
UC0
WC0
Description
Uncacheable Memory Type
Write-Combining Memory Type
Bits
0
1
Symbol
UC1
WC1
Description
Uncacheable Memory Type
Write-Combining Memory Type
Bits
32
33
WCn
UCn
Memory Type
0
0
No effect on cacheability or write-combining
1
0
Write-combining memory range (uncacheable)
0 or 1
1
Uncacheable memory range
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