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參數(shù)資料
| 型號(hào)： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁(yè)數(shù)： | 64/98頁(yè) |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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52
Model D Registers
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Figure 23. L2 Tag Information (AMD-K6-2E+ Processor)—EAX
Figure 24. L2 Tag Information (AMD-K6-
III
E+ Processor)—EAX
LRU (Least Recently
Used) Field
For the 4-way set associative L2 cache, each way has a 2-bit LRU
field for each sector. Values for the LRU field are 00b, 01b, 10b,
and 11b, where 00b indicates that the sector is “most recently
used,” and 11b indicates that the sector is “l(fā)east recently used”
(see Figure 25 on page 53). EAX[7:6] indicate the LRU
information for Way 0, EAX[5:4] for Way 1, EAX[3:2]
for
Way 2,
and EAX[1:0]
for
Way 3.
C
M
D
Reserved
Description
Tag data read or written
Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10
Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8
LRU
Two bits of LRU for each way
0
Tag
31
14
12
10 9
7
8
11
LRU
Line0ST
Line1ST
Symbol
Tag
Bit
31-14
7-0
13
C
M
D
Reserved
Description
Tag data read or written
Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10
Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8
LRU
Two bits of LRU for each way
0
Tag
15
31
14
12
10 9
7
8
11
LRU
Line0ST
Line1ST
Symbol
Tag
Bit
31-15
7-0
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