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| 型號： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁數(shù)： | 57/98頁 |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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Model D Registers
45
23913A/0—November 2000
Embedded AMD-K6 Processors BIOS Design Guide
Preliminary Information
Model D Registers
The AMD-K6-2E+ and AMD-K6-IIIE+ processors (Model D)
provide the twelve model-specific registers listed in Table 22.
The contents of ECX selects the MSR to be addressed by the
RDMSR and WRMSR instruction.
The AMD-K6-2E+ and AMD-K6-IIIE+ processors contain a split
Level-1 (L1) 64-Kbyte writeback cache organized as a separate
32-Kbyte instruction cache and a 32-Kbyte data cache with
two-way set associativity. The cache line size is 32 bytes, and
lines are read from memory using an efficient pipelined burst
read cycle. In addition, these processors also contain a 128-
Kbyte (AMD-K6-2E+ processor) or a 256-Kbyte (AMD-K6-IIIE+
processor), 4-way set associative, unified Level-2 (L2) cache.
Further performance gains are achieved by the implementation
of a write allocation scheme.
Table 22. Model-Specific Registers Supported by Model D
Register Name
Machine-Check Address Register
Machine-Check Type Register
Test Register 12
Time Stamp Counter
Mnemonic ECX Value
MCAR
MCTR
TR12
TSC
Description Comments
page 16
page 16
page 16
page 16
00h
01h
0Eh
10h
Identical on all models
Identical on all models
Identical on all models
Identical on all models
Adds L2 Disable bit (L2D) to Model
8/[F:8] implementation
Identical to Model 8/[F:8]
Identical to Model 8/[7:0]
Identical to Model 8/[F:8]
Standard-power implementation is
identical to Model 8/[F:8]. Low-
power implementation adds new
fields and renames BF to EBF.
Identical to Model 8/[F:8]
Identical to Model 9, but note dif-
fering L2 cache sizes on Model D.
New for Model D. Supported on
low-power versions only.
Extended Feature Enable Register
EFER
C000_0080h page 39
Write Handling Control Register
SYSCALL/SYSRET Target Address Register STAR
UC/WC Cacheability Control Register
WHCR
C000_0082h page 27
C000_0081h
C000_0085h page 30
page 22
UWCCR
Processor State Observability Register
PSOR
C000_0087h
page 34
1
,
page 46
2
Notes:
1.
2. Low-power versions only.
Standard-power versions only.
Page Flush/Invalidate Register
PFIR
C000_0088h page 36
Level-2 Cache Array Access Register
L2AAR
C000_0089h page 48
Enhanced Power Management Register
2
EPMR
C000_0086h page 54
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