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參數(shù)資料
| 型號(hào)： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁數(shù)： | 50/98頁 |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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38
Model 9 Registers
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Model 9 Registers
The AMD-K6-III processor (Model 9) provides the eleven model-
specific registers listed in Table 19.
The contents of ECX selects the MSR to be addressed by the
RDMSR and WRMSR instruction.
The AMD-K6-III processor contains a split Level-1 (L1)
64-Kbyte writeback cache organized as a separate 32-Kbyte
instruction cache and a 32-Kbyte data cache with two-way set
associativity. The cache line size is 32 bytes, and lines are read
from memory using an efficient pipelined burst read cycle. In
addition, the processor also contains a 256-Kbyte, 4-way set
associative, unified level-2 (L2) cache. Further performance
gains are achieved by the implementation of a write allocation
scheme.
Table 19. Model-Specific Registers Supported by Model 9
Register Name
Machine-Check Address Register
Machine-Check Type Register
Test Register 12
Time Stamp Counter
Mnemonic
MCAR
MCTR
TR12
TSC
ECX Value
00h
01h
0Eh
10h
Description
page 16
page 16
page 16
page 16
Comments
Identical on all models
Identical on all models
Identical on all models
Identical on all models
Adds L2 Disable bit (L2D) to
Model 8/[F:8] implementation
Identical to Model 8/[F:8]
Extended Feature Enable Register
EFER
C000_0080h
page 39
Write Handling Control Register
SYSCALL/SYSRET Target Address Regis-
ter
UC/WC Cacheability Control Register
Processor State Observability Register
WHCR
C000_0082h
page 27
STAR
C000_0081h
page 22
Identical to Model 8/[7:0]
UWCCR
PSOR
C000_0085h
C000_0087h
page 30
page 34
Identical to Model 8/[F:8]
Identical to Model 8/[F:8]
Identical to Model 8/[F:8]. The
invalidate and flush operations
affect both the L1 and L2 caches
on the AMD-K6-
III
processor.
New for Model 9
Page Flush/Invalidate Register
PFIR
C000_0088h
page 36
Level-2 Cache Array Access Register
L2AAR
C000_0089h
page 40
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