參數(shù)資料
型號: 23913A
英文描述: Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF)
中文描述: 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記? 1.33MB(PDF格式)
文件頁數(shù): 58/98頁
文件大小: 1365K
代理商: 23913A
46
Model D Registers
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Processor State Observability Register (PSOR) (Low-Power Versions)
The low-power versions of the AMD-K6-2E+ and AMD-K6-IIIE+
processors provide the Processor State Observability Register
(PSOR) as defined in Figure 17.
Note:
Standard-power versions of Model D support the PSOR as
defined on page 34.
The PSOR register is MSR C000_0087h.
.
Figure 17.
Processor State Observability Register (PSOR
) (Model D Low-Power Versions)
PBF[2:0] Field
This read-only field contains the BF divisor values externally
applied to the processor BF[2:0] pins. These input BF values are
sampled by the processor during the falling transition of
RESET.
Note:
This BF divisor value may be different than the BF divisor
value supplied to the processor’s internal PLL.
VID Field
This read-only field contains the Voltage ID bits driven to the
processor VID[4:0] pins at RESET. These bits are initialized to
01010b and driven on the VID[4:0] pins at RESET.
Note:
Low-power AMD-K6-2E+ and AMD-K6-IIIE+ processors
support
AMD PowerNow! technology,
dynamic alteration of the processor’s core voltage. See
“Enhanced Power Management Register (EPMR) (Low-
Power Versions)” on page 54 for information on
programming the VID[4:0] pins.
which
enables
2
0
63
EBF[2:0]
Reserved
Symbol
NOL2
STEP
EBF
Description
No L2 Functionality
Processor Stepping
Effective Bus Frequency Divisor
Bits
8
7-4
2-0
3
4
STEP
7
8
N
O
L
2
9
VID
PBF[2:0]
16
20
23
21
15
24
Symbol
PBF
VID
Description
Pin Bus Frequency Divisor
Voltage ID
Bits
23-21
20-16
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