參數(shù)資料
型號(hào)： 23913A
英文描述： Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF)
中文描述： 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式）
文件頁(yè)數(shù)： 46/98頁(yè)
文件大?。?/td> 1365K
代理商： 23913A
34
Model 8/[F:8] Registers
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Processor State Observability Register (PSOR)
Models 8/[F:8], 9, and standard-power versions of Model D
provide the Processor State Observability Register (PSOR) as
defined in Figure 8. The PSOR register is MSR C000_0087h.
Note:
See page 46 for definitions of the PSOR bit fields for low-
power Model D processors.
.
Figure 8.
Processor State Observability Register (PSOR
) (Models 8/[F:8], 9, and Standard-Power D)
NOL2 Bit
This read-only bit indicates whether the processor contains an
L2 cache.
Note:
This bit is always set to 1 for Model 8/[F:8].
Note:
This bit is always set to 0 for Models 9 and D.
STEP Field
This read-only field contains the stepping ID. This is identical to
the value returned by the CPUID standard function 1 in
EAX[3:0].
BF Field
This read-only field contains the value of the BF signals
sampled by the processor during the falling transition of
RESET, which allows the BIOS to determine the frequency of
the host bus.
I
The core frequency must first be known, which can be
determined using the Time Stamp Counter method (See
“Time Stamp Counter (TSC)” on page 16).
The core frequency is then divided by the processor-clock to
bus-clock ratio as determined by the BF field of the PSOR
register (see Table 17 and Table 18 on page 35).
The result is the frequency of the processor bus.
I
I
2
0
63
BF
Reserved
Description
No L2 Functionality
Processor Stepping
Bus Frequency Divisor
Symbol
NOL2
STEP
BF
Bit
8
7-4
2-0
3
4
STEP
7
8
9
N
O
L
2
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