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參數(shù)資料
| 型號(hào)： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁(yè)數(shù)： | 38/98頁(yè) |
| 文件大小： | 1365K |
| 代理商： | 23913A |
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26
Model 8/[F:8] Registers
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
samples the EWBE# signal. If EWBE# is sampled negated, the
processor delays the commitment of write cycles to processor
cache lines in the modified state or exclusive state until EWBE#
is sampled asserted.
This setting provides performance comparable to, but slightly
less than, the performance obtained when GEWBED equals 1
because some degree of write ordering is maintained.
Slowest Performance.
If GEWBED equals 0 and SEWBED equals 0,
the processor enforces strong ordering for all internal and
external write cycles. In this setting, the processor assumes, or
speculates
, that strong order must be maintained between writes
to the merge buffer and writes that hit the processor’s cache.
Once the merge buffer is written out to the processor’s bus, the
EWBE# signal is sampled. If EWBE# is sampled negated, the
processor delays the commitment of write cycles to processor
cache lines in the modified state or exclusive state until EWBE#
is sampled asserted.
This setting is the default after RESET and provides the lowest
performance of the three settings because full write ordering is
maintained.
Write Ordering and Performance.
Table 14 summarizes the three
settings of the EWBEC field, along with the effect of write
ordering and performance.
Enforcing complete write ordering in a uniprocessor system is
usually not necessary. In order to achieve the highest level of
performance while still maintaining support for the EWBE#
signal, AMD recommends that the BIOS set EFER[3:2] to 01b
(close-to-best performance). Many uniprocessor systems do not
support the EWBE# signal, in which case AMD recommends
that the BIOS set EFER[3:2] to 10b or 11b (best performance).
Table 14. Write Ordering and Performance Settings for EFER Register
EFER[3] (GEWBED)
1
EFER[2] (SEWBED)
0 or 1
Write Ordering
None
All except UC/WC
All
Performance
Best
Close-to-Best
Slowest
0
1
0 (Default)
0 (Default)
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