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參數(shù)資料
| 型號： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁數(shù)： | 81/98頁 |
| 文件大小： | 1365K |
| 代理商： | 23913A |
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Additional Considerations
69
23913A/0—November 2000
Embedded AMD-K6 Processors BIOS Design Guide
Preliminary Information
Additional Considerations
Software Timing Dependencies Relative to Memory Controller Setup
Processors in the K86 family differ from other processors with
regards to instruction latencies and the order or priority of
processor bus cycles. Timing-dependent software that relies on
the specific latencies of other processors should be re-tested for
proper operation with the K86 processor. In addition, re-testing
should be performed on components with variable timing (such
as memory modules, oscillators, and timers).
Particular attention should be paid to memory-setup
subroutines that determine the type of DRAM in the system.
Some chipsets may not tolerate a DRAM mode change (such as,
EDO to SDRAM) on the same clock as a DRAM refresh cycle.
For example some chipsets do not tolerate having its memory
refresh enabled prior to changing memory mode types. Refresh
should only be enabled after the memory type has been
determined.
Note:
The BIOS for the K86 family of processors should enable the
write allocate mechanisms only after performing any
memory sizing or typing algorithms.
Pipelining Support
All production models and steppings of the AMD-K6 processor
support the WAELIM form of write allocate, which is the only
form of write allocate that should be enabled. AMD does not
recommend enabling the obsolete form of write allocate
(WCDE) because system performance can be degraded by
doing so.
Early implementations of the AMD-K6 processor did not
support the WHCR register and therefore did not support the
WAELIM form of write allocate. WCDE was the only form of
write allocate supported, which required the chipset to assert
KEN# for cacheable memory write cycles. Because KEN# is
sampled by the processor on the clock edge on which the first
BRDY# or NA# is sampled asserted, some chipsets that
supported the WCDE form of write allocate did not assert NA#
during write cycles in order to prevent the processor from
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