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| 型號： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁數(shù)： | 51/98頁 |
| 文件大小： | 1365K |
| 代理商： | 23913A |
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Model 9 Registers
39
23913A/0—November 2000
Embedded AMD-K6 Processors BIOS Design Guide
Preliminary Information
Extended Feature Enable Register (EFER)
Figure 10 shows the format of the EFER register for models 9
and D, and Table 20 defines the function of each bit of the
EFER register. The EFER register is MSR C000_0080h.
Note:
Bits 3:0 of the EFER register in models 9 and D are identical
to the implementation of these bits in Model 8/[F:8]. For
models 9 and D, the L2 Disable bit (L2D), EFER[4], is
added. The complete new register description is included in
this section.
Figure 10. Extended Feature Enable Register (EFER) (Models 9 and D)
Note:
Setting L2D to 1 does not guarantee cache coherency. To
ensure coherency, the processor’s caches must be disabled
(by setting the CD bit of the CR0 register to 1), then flushed
prior to setting L2D to 1.
Table 20. Extended Feature Enable Register (EFER) Definition (Models 9 and D)
Bit Description
R/W Function
Writing a 1 to any reserved bit causes a general protection fault to occur. All
reserved bits are always read as 0.
If L2D is set to 1, the L2 cache is completely disabled. This bit is provided for
debug and testing purposes. For normal operation and maximum performance,
this bit must be set to 0 (this is the default setting following reset).
This 2-bit field controls the behavior of the processor with respect to the ordering
of write cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE#
Disable (GEWBED) and Speculative EWBE# Disable (SEWBED), respectively.
DPE must be set to 1 to enable data prefetching (this is the default setting follow-
ing reset). If enabled, cache misses initiated by a memory read within a 32-byte
cache line are conditionally followed by cache-line fetches of the other line in the
64-byte sector.
System Call Extension (SCE)
R/W
SCE must be set to 1 to enable usage of the SYSCALL and SYSRET instructions.
63–5
Reserved
R
4
L2 Disable (L2D)
R/W
3-2
EWBE Control (EWBEC)
R/W
1
Data Prefetch Enable (DPE)
R/W
0
1
0
63
S
C
E
Reserved
Description
L2 Disable
EWBE Control
Data Prefetch Enable
System Call Extension
2
3
4
D
P
E
EWBEC
L
2
D
Symbol
L2D
EWBEC
DPE
SCE
Bit
4
3-2
1
0
5
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