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參數資料
| 型號： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設計指南應用筆記？ 1.33MB（PDF格式） |
| 文件頁數： | 61/98頁 |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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Model D Registers
49
23913A/0—November 2000
Embedded AMD-K6 Processors BIOS Design Guide
Preliminary Information
The L2AAR register is MSR C000_0089h.
The operation that is performed on the L2 cache is a function of
the instruction executed—RDMSR or WRMSR—and the
contents of the EDX register. The EDX register specifies the
location of the access, and whether the access is to the L2 cache
data or tags (refer to Figure 20 on page 50 for the AMD-K6-2E+
processor and Figure 21 on page 50 for the AMD-K6-IIIE+
processor).
Figure 19 shows the L2 cache sector and line organization. If bit
5 (refer to Figure 20 for the AMD-K6-2E+ processor and Figure
21 for the AMD-K6-IIIE+ processor) of the address of a cache
line equals 1, then this cache line is stored in Line 1 of a sector.
Similarly, if bit 5 of the address of a cache line equals 0, then
this cache line is stored in Line 0 of a sector.
Figure 19. L2 Cache Sector and Line Organization (same as Figure 12)
Bit 15 of EDX, which is the most significant bit of the Set field,
is not used for the AMD-K6-2E+ because there are half as many
sets implemented on the AMD-K6-2E+ (512 sets) as the
AMD-K6-IIIE+ processor (1024 sets). Bit 20 of EDX (T/D)
determines whether the access is to the L2 cache data or tag.
Table 24 on page 51 describes the operation that is performed
based on the instruction and the T/D bit.
Upper Dword
Lower Dword
Octet 0
Line 1
Octet 1
Octet 2
Octet 3
Upper Dword
Lower Dword
Line 0
Sector
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