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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 13/86頁 |
| 文件大小： | 1297K |
| 代理商： | 84225 |
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MD400183/A
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scrambled data into MLT3 ternary format. The transmitter
then preshapes the output and drives the twisted pair
cable. For FX operation, the encoded data is converted to
NRZI format which drives a binary (two level) signal to the
fiber transceiver interface (PMD).
On the receive side for 100BaseTX operation, the TX
receiver removes any high frequency noise from the input,
equalizes the input signal to compensate for the low pass
effects of the cable, and qualifies the data with a squelch
algorithm. The TX receiver then converts the data from
MLT3 coded twisted pair levels to internal digital levels.
The output of the receiver then goes to a clock and data
recovery block which recovers a clock from the incoming
data, uses the clock to latch in valid data into the device,
and converts the data back to NRZ data. The data is then
unscrambled and decoded by the 4B5B decoder and
descrambler, respectively, and output to an external
Ethernet controller by the controller interface. 100Base
FX receiver operation is the same as TX except there is no
equalizer, descrambler, and has a seperate ECL receiver.
10 Mbps operation is similar to the 100 Mbps operation,
except:
There is no scrambler/descrambler.
The encoder/decoder is Manchester instead of 4B5B.
The data rate is 10 Mbps instead of 100 Mbps.
The twisted pair symbol data is two level Manchester
instead of ternary MLT3.
The FX interface is disabled for 10 Mbps operation.
The AutoNegotiation block automatically configures each
channel for either 100BaseTX or 10BaseT and either Full
or Half Duplex operation. This configuration is based on
the capabilities selected for the channel and capabilities
detected from the remote device connected to the
channel.
The Management Interface (the MI serial port) is a two pin
bidirectional link through which configuration inputs can be
set and channel status outputs read.
Each block plus the operating modes are described in
more detail in the following sections. Since the 84225 can
operate as a 100BaseFX, 100BaseTX or a 10BaseT
device, each of the following sections describes the
performance in both 100 and 10 Mbps modes.
2.2 CONTROLLER INTERFACE
2.2.1 General
The 84225 has three interfaces to an external controller:
Media Independent Interface (MII), Reduced pin MII
(RMII), and Five Bit Interface (FBI). MII is the default
interface. RMII is selected by asserting the RMII_EN pin,
a global control (all channels effected). FBI is selected, on
a per port basis, by setting the bypass encoder bit in the
MI serial port Channel Configuration register (Register
17).
2.2.2 MII - 100 Mbps
The MII is a nibble wide packet data interface defined in
IEEE 802.3. The 84225 meets all MII requirements
outlined in IEEE 802.3. The 84225 can directly connect,
without external logic, to any Ethernet controller or other
device that also complies with the IEEE 802.3 MII
specification. The MII frame format is shown in Figure 3.
The MII consists of four transmit data bits (TXD[3:0]),
transmit clock (TXCLK), transmit enable (TXEN), transmit
error (TXER), four receive data bits (RXD[3:0]), receive
clock (RXCLK), carrier sense (CRS), receive data valid
(RXDV), receive data error (RXER), and collision (COL).
The transmit clock (TXCLK) is a common signal for all four
channels. All other signals are separate for each channel.
The transmit and receive clocks operate at 25 MHz in 100
Mbps mode.
On the transmit side, the TXCLK output runs continuously
at 25 MHz. When no data is to be transmitted, TXEN must
be deasserted. While TXEN is deasserted, TXER and
TXD[3:0] are ignored and no data is clocked into the
device. When TXEN is asserted on the rising edge of
TXCLK, data on TXD[3:0] is clocked into the device on
rising edges of the TXCLK output clock. TXD[3:0] input
data is nibble wide packet data whose format is specified
in IEEE 802.3 and shown in Figure 3. When all packet
data has been latched into the device, TXEN must be
deasserted on the rising edge of TXCLK.
TXER is also clocked in on rising edges of the TXCLK
clock. TXER is a transmit error signal which, when
asserted, will substitute an error nibble in place of the
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