參數(shù)資料
型號： 84225
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁數(shù)： 30/86頁
文件大?。?/td> 1297K
代理商： 84225
30
MD400183/A
84225
2.24 REPEATER MODE
The 84225 has one predefined repeater mode which can
be enabled by asserting the REPEATER pin. When this
mode is enabled the device operation is altered as follows:
TXEN to CRS loopback is disabled.
2.25 MI SERIAL PORT
2.25.1 Signal Description
The MI serial port has five pins, MDC, MDIO, and
PHYAD[4:2]. MDC is the serial shift clock input. MDIO is a
bidirectional data I/O pin. PHYAD[4:2] are physical
address pins.
Pins PHYAD[4:2] set the three most significant bits of the
PHY address. The two least significant bits of the PHY
address are set internally to match the channel number,
as shown in Table 5.
Table 5. PHYAD[1:0] Settings
2.25.2 Timing
Figure 10 shows a timing diagram for a MI serial port
cycle.
The MI serial port is idle when at least 32 continuous 1's
are detected on MDIO and remains idle as long as
continuous 1's are detected. During idle, MDIO is in the
high impedance state. When the MI serial port is in the idle
state, a 01 pattern on the MDIO pin initiates a serial shift
cycle. Data on MDIO is then shifted in on the next 14 rising
edges of MDC (MDIO is high impedance). If the register
access mode is not enabled, on the next 16 rising edges
of MDC, data is either shifted in or out on MDIO,
depending on whether a write or read cycle was selected
with the bits READ and WRITE. After the 32 MDC cycles
have been completed, one complete register has been
PHYAD1
1
PHYAD0
1
Channel 3
Channel 2
1
0
Channel 1
0
1
Channel 0
0
0
read/written, the serial shift process is halted, data is
latched into the device, and MDIO goes into high
impedance state. Another serial shift cycle cannot be
initiated until the idle condition (at least 32 continuous 1's)
is detected.
2.25.3 Multiple Register Access
Multiple registers can be accessed on a single MI serial
port access cycle with the multiple register access feature.
The multiple register access feature can be enabled by
setting the multiple register access enable bit in the
Global Configuration Register for all channels.
When multiple register access is enabled, all registers can
be accessed on a single MI serial port access cycle by
setting the register address to 11111 during the first 16
MDC clock cycles. There is no actual register residing in
register address location 11111.
When the register address is set to 11111, all eleven
registers are accessed for all four channels on the 704
rising edges of MDC (4 x 11 x 16) that occur after the first
16 MDC clock cycles of the MI serial port access cycle.
The registers are accessed in numerical order from 0 to
20 for each channel and from channel 0 to 3. After all 720
MDC clocks have been completed, all the registers have
been read/written, and the serial shift process is halted,
data is latched into the device, and MDIO goes into high
impedance state. Another serial shift cycle cannot be
initiated until the idle condition (at least 32 continuous 1's)
is detected.
2.25.4 Bit Types
Since the serial port is bidirectional, there are many types
of bits. The bit type definitions are summarized in Table 6.
Write bits (W) are inputs during a write cycle and are high
impedance during a read cycle. Read bits (R) are outputs
during a read cycle and high impedance during a write
cycle. Read/Write bits (R/W) are actually write bits that
can be read out during a read cycle. R/WSC bits are R/W
bits that are self clearing after a set period of time or after
a specific event has completed. R/LL bits are read bits
that latch themselves when they go low, and they stay
latched low until read. After they are read, they are reset
high. R/LH bits are the same as R/LL bits, except that they
latch high. R/LT are read bits that latch themselves
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