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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 24/86頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | 84225 |
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24
MD400183/A
84225
2.12 START OF PACKET
2.12.1 100 Mbps
Start of packet for 100 Mbps mode is indicated by a
unique Start of Stream Delimiter (SSD). The SSD pattern
consists of the two /J/K/ 5B symbols inserted at the
beginning of the packet in place of the first two preamble
symbols, as defined in IEEE 802.3 Clause 24 and shown
in Table 2 and Figure 2.
The transmit SSD is generated by the 4B5B encoder and
the /J/K/ symbols are inserted by the 4B5B encoder at the
beginning of the transmit data packet in place of the first
two 5B symbols of the preamble, as shown in Figure 2.
The receive pattern is detected by the 4B5B decoder by
examining groups of 10 consecutive code bits (two 5B
words) from the descrambler. Between packets, the
receiver will be detecting the idle pattern, which is 5B /I/
symbols. While in the idle state, CRS and RXDV are
deasserted.
If the receiver is in the idle state and 10 consecutive code
bits from the receiver consist of the /J/K/ symbols, the start
of packet is detected, data reception is begun, CRS and
RXDV are asserted, and /5/5/ symbols are substituted in
place of the /J/K/ symbols.
If the receiver is in the idle state and 10 consecutive code
bits from the receiver consist of a pattern that is neither /I/
I/ nor /J/K/ symbols but contains at least 2 non-contiguous
0's, then activity is detected but the start of packet is
considered to be faulty and a False Carrier Indication (also
referred to as bad SSD) is signalled to the controller
interface. When False Carrier is detected CRS is
asserted, RXDV remains deasserted, RXD[3:0]=1110
while RXER is asserted, and the bad SSD bit is set in the
MI serial port Channel Status Output register. Once a
False Carrier Event is detected, the idle pattern (two /I/I/
symbols) must be detected before any new SSD’s can be
sensed.
If the receiver is in the idle state and 10 consecutive code
bits from the receiver consist of a pattern that is neither /I/
I/ nor /J/K/ symbols but does not contain at least 2 non
contiguous 0's, the data is ignored and the receiver stays
in the idle state.
2.12.2 10 Mbps
Since the idle period in 10 Mbps mode is defined to be no
data on the TP inputs, then the start of packet for 10 Mbps
mode is detected when valid data is detected by the TP
squelch circuit. When start of packet is detected, CRS is
asserted as described in The CONTROLLER INTERFACE
Section. Refer to the TP Squelch - 10 Mbps Section for
the algorithm for valid data detection.
2.13 END OF PACKET
2.13.1 100 Mbps
End of packet for 100 Mbps mode is indicated by an End
of Stream Delimiter (referred to as ESD). The ESD pattern
consists of the two /T/R/ 4B5B symbols inserted after the
end of the packet, as defined in IEEE 802.3 Clause 24
and shown in Table 2 and Figure 2.
The transmit ESD is generated by the 4B5B encoder and
the /T/R/ symbols are inserted by the 4B5B encoder after
the end of the transmit data packet, as shown in Figure 2.
The receive ESD pattern is detected by the 4B5B
decoder by examining groups of 10 consecutive code bits
(two 5B words) from the descrambler during valid packet
reception to determine whether there is an ESD.
If the 10 consecutive code bits from the receiver during
valid packet reception consist of the /T/R/ symbols, the
end of packet is detected, data reception is terminated,
CRS and RXDV are deasserted, and /I/I/ symbols are
substituted in place of the /T/R/ symbols.
If 10 consecutive code bits from the receiver during valid
packet reception do not consist of /T/R/ symbols, but
consist of /I/I/ symbols instead, the packet is considered
to have been terminated prematurely and abnormally.
When this premature end of packet condition is detected,
RXER remains asserted for the nibble associated with the
first /I/ symbol detected and then RXER and CRS and
RXDV are all deasserted. Premature end of packet
condition is also indicated by setting the ESD error bit in
the MI serial port Channel Status Output register.
2.13.2 10 Mbps
The end of packet for 10 Mbps mode is indicated with the
SOI (Start of Idle) pulse. The SOI pulse is a positive
double wide pulse containing a Manchester code violation
inserted at the end of every packet.
The transmit SOI pulse is generated by the TP transmitter
and inserted at the end of the data packet after TXEN is
deasserted. The transmitted SOI output pulse at the TP
output is shaped by the transmit waveshaper to meet the
pulse template requirements specified in IEEE 802.3
Clause 14 and shown in Figure 6.
The receive SOI pulse is detected by the TP receiver by
sensing missing data transitions. Once the SOI pulse is
detected, data reception is ended and CRS and RXDV are
deasserted.
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