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參數(shù)資料
| 型號(hào)： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 33/86頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | 84225 |
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MD400183/A
33
84225
The structure and bit definition of the Status Register is
shown in Table 10. This register contains device
capabilities and status output information and its bit
definition complies with the IEEE 802.3 specifications.
The structure and bit definition of the PHY ID Register 1
and PHY ID Register 2 is shown in Table 11 and Table 12,
respectively. These registers contain an identification
code unique to the 84225 and their bit definition complies
with the IEEE 802.3 specifications.
The structure and bit definition of the Auto Negotiation
Advertisement and Auto Negotiation Remote End
Capability registers is shown in Table 13 and Table 14,
respectively. These registers are used by the Auto
Negotiation algorithm and their bit definition complies with
the IEEE 802.3 specifications.
The structure and bit definition of the Global Configuration
Register is shown in Table 15. This register is common for
all four channels. It stores various configuration inputs.
The structure and bit definition of the Channel
Configuration Register is shown in Table 16. This register
stores various configuration inputs unique to each
channel.
The structure and bit definition of the Channel Status
Output Register is shown in Table 17. This register
contains output status information from each channel.
The structure and bit definition of the Global Interrupt
Mask Register is shown in Table 18. This register is
common for all four channels. Bit 7 is the interrupt
indication. The 7 least significant bits are the Mask bits for
the R/LT status bits in the Channel Status Output
Register.
Register 20 in Table 19 is reserved for factory use only. All
bits must be set to the pre-set default states shown for
normal operation.
2.25.7 Invalid Registers
The registers in locations 6-15 and 21-31 are not
implemented on the device, hence unused. When an
unused register is read, the value returned can be
configured to be either all 0s or all 1s by appropriately
pinstrapping the REGDEF pin.
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