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參數(shù)資料
| 型號(hào)： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁(yè)數(shù)： | 23/86頁(yè) |
| 文件大小： | 1297K |
| 代理商： | 84225 |
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MD400183/A
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84225
The SD/FXEN input goes directly to a comparator. The
comparator compares the input waveform against the
internal ECL threshold level to produce a digital signal with
internal logic levels. The output of the signal detect
comparator then goes to the link integrity and squelch
blocks. If the signal detect input is asserted, the channel
is placed in the Link Pass state and the input data on
FXIP/FXIN is determined to be valid. If the signal detect
input is deasserted, the channel is placed in the Link Fail
state and the input data on FXIP/FXIN is determined to be
invalid.
The SD_THR pin adjusts the ECL trip point of the SD/
FXEN input. When the SD_THR pin is tied to a voltage
between GND and GND+0.45V the trip point of the SD
ECL input buffer is internally set to VCC-1.3V When
SD_THR pin is set to a voltage greater than GND+0.85v,
the trip point of the SD SD/FXEN ECL input buffer is set to
the voltage that is applied to the SD_THR pin. The trip
level for the SD/FXEN input buffer must be set to VCC-
1.3V Having external control of the SD/FXEN buffer trip
level with the SD_THR pin allows this trip level to be
referenced to an external supply which facilitates
connection to both 3.3V and 5V external fiber optic
transceiver. If the device is to be connected to a 3.3V
external fiber optic transceiver, then SD_THR should be
tied to GND. If the device is to be connected to a 5V
external fiber optic transceiver, then SD_THR needs to be
tied to VCC-1.3V and this can be done so with an external
resistor divider. Refer to the Applications section for more
details on connections to external fiber optic transceivers.
2.10.5 Fiber Interface Disable
The Fiber Interface will be disabled if the SD/FXEN pin is
tied to GND. Disabling the Fiber Interface automatically
enables the TP interface.
2.10.6 Far End Fault
Each channel has the Far End Fault capability, referred to
as FEF defined in IEEE 802.3 specifications. FEF is a
method by which the Fiber Interface can signal a fault to a
remote device by transmitting an idle pattern consisting of
84 ‘1’s followed by a single ‘0’ repeatedly (idle period
normally has all 1’s). FEF was specified in IEEE 802.3
because FX lacks the AutoNegotiation capability to signal
a remote fault to another station.
FEF can only be made operational only when the Fiber
Interface is enabled. In the device default state with the
Fiber Interface enabled, FEF is disabled, but it can be
enabled by setting the FEF select bit in the MI serial port
Global Configuration register. When FEF is enabled, (1) a
‘0’ is transmitted after each group of 84 ‘1’s repeatedly
during idle if the SD/FXEN pin is deasserted, and (2) if an
FEF stream is detected by the receiver for 3 consecutive
intervals, the remote fault bit is set in the MI serial port
Status register and the LED0 output pin is asserted.
2.11 COLLISION
2.11.1 100 Mbps
Collision occurs whenever transmit and receive occur
simultaneously while the device is in Half Duplex. Collision
is sensed whenever there is simulaneous transmission
(packet transmission on TPOP/N) and reception (non idle
symbols detected on receive input). When collision is
detected:
The COL output is asserted.
TP data continues to be transmitted on twisted pair
outputs.
TP data continues to be received on twisted pair inputs.
Internal CRS loopback is disabled.
Once collision starts, CRS is asserted and stays asserted
until the receive and transmit packets that caused the
collision are terminated.
The collision function is disabled if the device is in the Full
Duplex mode, is in the Link Fail state, or if the device is in
the diagnostic loopback mode.
2.11.2 10 Mbps
Collision in 10 Mbps mode is identical to the 100 Mbps
mode, except:
Reception is detemined by the 10 Mbps squelch
criteria.
RXD[3:0] outputs are forced to all 0's.
Collision is asserted when the SQE test is performed.
Collision is asserted when the jabber condition has
been detected.
2.11.3 Collision Test
The controller interface collision signal, COL, can be
tested by setting the collision test register bit in the MI
serial port Control register. When this bit is set, TXEN is
looped back onto COL and the TP outputs are disabled.
2.11.4 Collision Indication
Collision can be programmed to appear on the LED2 pin
by appropriately setting the LED definition bits in the MI
serial port Global Configuration register. The LED
DRIVERS Section describes the programmable LED
definition bit settings. When the LED2 pin is programmed
to be a collision detect output, the pin is asserted low for
100 mS every time a collision occurs.
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