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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 53/86頁 |
| 文件大小： | 1297K |
| 代理商： | 84225 |
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MD400183/A
53
84225
The termination network on the FXIP/FXIN inputs of the
84225 must be modified for operation with 5V modules by
adding a third resistor as a “tap” on the pulldown leg, as
shown in Figure 15. This divides down the voltage seen at
the input of the 84225 so that it does not exceed the
range of the input buffer. The pullup resistor
recommended by the 5V module supplier will generally
remain the same - usually about 82.5 Ohms to the 5V
supply. The normally recommended 125 Ohm pulldown
resistor must be split into two. The values of this new pair
should be 52.3 Ohms connected to the pullup resistor and
73.2 Ohms connected from the 52.3 Ohm resistor to
ground, providing a voltage divider function at the junction
of the pair. The junction of these two resistors should be
connected to the FXIP/FXIN and SD_[3:0]/FXEN_[3:0]
inputs of the 84225. This will provide a High PECL logic
level of 2.36V and a low of 1.92V which is sufficient for
operation of the 84225. An interface suitable for
operation wit 5V fiber transceiver modues is shown below
in Figure 15.
Figure 15. FX Interface to 5V Fiber Modules
4.6 MII CONTROLLER INTERFACE
4.6.1 General
The MII controller interface allows the 84225 to connect to
any external Ethernet controller without any glue logic,
provided that the external Ethernet controller has an MII
interface that complies with IEEE 802.3 as shown in
Figure 12 and Figure 13.
The 84225 also offers RMII (Reduced MII) interface as a
selectable option for use with controllers (MACs)
supporting RMII operation. By holding the RMII_EN pin
high, the RMII interface is enabled, cutting the required
interface signals from 16 to 6. This is a significant savings
in board interconnect for high port count systems.
For normal MII operation the RMII_EN pin should be tied
to GND. Refer to the RMII description in Section 2 for
details of the interface operation.
4.6.2 Clocks
Standard Ethernet controllers with an MII use TXCLK to
clock data in on inputs TXD[3:0]. TXCLK is specified in
IEEE 802.3 and on the 84225 to be an output. The 84225
requires a 25 MHz reference frequency in MII mode, and
50 MHz in RMII mode. This reference frequency must be
applied to the CLKIN pin. CLKIN generates TXCLK inside
the 84225; thus, data can be clocked into the 84225 on
the rising edge of output clock TXCLK or on the rising
edge of input clock CLKIN.
If a nonstandard controller is used to interface to the
84225, or in Repeater Applications, there may be a need
to clock TXD[3:0] into the 84225 on the rising edge
CLKIN. Where CLKIN is used as the input clock, TXCLK
can be left open or used for another purpose.
4.6.3 MII Disable
The MII outputs can be placed in the high impedance
state and inputs disabled by setting the MII disable bit in
the MI serial port Control register. When this bit is set to
the disable state, the TP and FX outputs are both
disabled and transmission is inhibited. The default value
of this bit when the device powers up or is reset is
dependent on the device address. If the device address
latched into PHYAD[4:0] at reset is 11111, it is assumed
that the device is being used in applications where there
maybe more than one device sharing the MII bus, like
external PHY’s or adapter cards, so the device powers up
with the MII interface disabled. If the device address
latched into PHYAD[4:0] at reset is not 11111, it is
assumed that the device is being used in an application
where it is the only device on the MII bus, like hubs, so the
device powers up with the MII interface enabled.
4.7 FBI CONTROLLER INTERFACE
The FBI (Five Bit Interface) controller interface has the
same characteristics of the MII except that the data path
is ive bits wide, instead of 4 bits wide per the MII. The ive
bit wide data path is automatically enabled when the
4B5B encoder is bypassed. Because of this encoder/
decoder bypass, the FBI is used primarily for repeaters or
3.3V
Transceiver
VDD = 3.3V
FXOP
FXON
FXIP
FXIN
SD/FXEN
SD_THR
T5V Fiber
RD
RD-
VDD = 5V
TD
TD-
SD
82.5
15K
10K
73.2
61.9
261
VDD = 5V
52.3
82.5
52.3
73.2
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