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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 84/86頁 |
| 文件大小： | 1297K |
| 代理商： | 84225 |
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84
MD400183/A
84225
Ordering Information
Q
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
Q – 0
°
C to +70
°
C
Quad 100 Base-TX/FX10 Base-T
Physical Layer Device (PHY)
84225
Q
Q = Plastic Quad
Flat Pack
Z
/
PRODUCT REV
Revision History
March 2, 1999: MD400183/– has been changed to MD400183/A
Global: References to JAM has been changed to AD_REV, and MDINT has been changed to REGDEF.
March 2, 1999
Page 6, Pin Description
- Pin #98, Row has been completely changed.
Page 7, Pin Description
- Pin #110, I/O, I Pulldown has been changed to I.
Page 8, Pin Description
- Pin #101, Pin Name RMII_EN has been changed to RMII_EN.
Page 11, Block Diagram
- References to JAM and MDINT have been change to AD_REV and REGDEF, respectively.
Page 33, 2.25.7 Invalid Registers
- Section 2.25.7 Invalid Registers is new.
Page 35, Table 7. MI Serial Port Structure
- Symbol REGAD4[4:0] Definition, copy, ...If REGDEF pin asserted and... has been deleted.
Page 36 Table 8. MI Serial Port Register Map
- Bit x.7, 18 Channel Status Output, INT has been changed to 0.
- Bit x.10, 4 AutoNegot. Advertisement, 0 has been changed to PAUSE.
- Bit x.10, 5 AutoNegot. Remote Capability, 0 has been changed to PAUSE.
This document is subject to changed without notice. SEEQ Technology Incorporated assumes no
responsibility for any errors contained herein.
Copyright by SEEQ Technology Incorporated, All Rights Reserved.
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