參數(shù)資料
型號(hào)： 84225
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁(yè)數(shù)： 35/86頁(yè)
文件大?。?/td> 1297K
代理商： 84225
MD400183/A
35
84225
3.0 REGISTER DESCRIPTION
Table 7. MI Serial Port Structure
MI Registers - Address and Default Value
<Idle>
IDLE
<Start>
ST[1:0]
<Read>
READ
<Write>
WRITE
<PHY Addr.>
PHYAD[4:0]
<Reg. Addr.>
REGAD[4:0]
<Turnaround>
TA[1:0]
<Data>
D[15:0]
REGAD
00000
00001
00010
00011
00100
00101
10000
10001
10010
Name
Control Register
Status Register
PHY ID 1 Register
PHY ID 2 Register
Auto Negotiation Advertisement Register
Auto Negotiation Remote Capability Register
Reserved
Reserved
Channel Status Output Register
Default
(Hex Code)
3000
7809
0016
F840
01E1
0000
0008
0002
0340/0240/
0140/0040
007F
0000
10011
10100
Reserved
Reserved
Symbol
Name
Definition
R/W
IDLE
Idle Pattern
These bits are an idle pattern. Device will not initiate an MI cycle until it
detects at least 32 1's.
W
ST[1:0]
Start Bits
When ST[1:0]=01, a MI serial port access cycle starts.
W
READ
Read Select
1 = Read Cycle
W
WRITE
Write Select
1 = Write Cycle
W
PHYAD[4:0]
Physical Device
Address
When PHYAD[4:2] bits match the PHYAD[4:2] pins, the MI serial port is
selected for operation. PHYAD[1:0] is used for channel selection:
PHYAD [1:0]=11 For Channel 3
PHYAD [1:0]=10 For Channel 2
PHYAD [1:0]=01 For Channel 1
PHYAD [1:0]=00 For Channel 0
W
REGAD4[4:0]
Register Address
If REGAD[4:0]=00000-11100, these bits determine the specific register from
which D[15:0] is read/written. If multiple register access is enabled and
REGAD[4:0]=11111, all registers are read/written in a single cycle.
W
TA[1:0]
Turnaround Time
These bits provide some turnaround time for MDIO
When READ=1, TA[1:0]=Z0
When WRITE=1, TA[1:0]=ZZ
R/W
D[15:0]+
Data
These 16 bits contain data to/from one of the eleven registers selected by
register address bits REGAD[4:0].
R or W
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