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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 54/86頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | 84225 |
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54
MD400183/A
84225
other applications where the PHY encoding/decoding
function is not needed. For more details about the FBI,
see the Non-MII Based Repeaters Section.
4.8 REPEATER APPLICATIONS
4.8.1 MII Based Repeaters
The 84225 can be used as the physical interface for MII
based repeaters by using the standard MII/RMII as the
interface to the repeater core.
For most repeaters, it is necessary to disable the internal
CRS loopback. This can be done by asserting the
repeater input of the chip.
For some particular types of repeaters, it may be
desirable to either enable or disable AutoNegotiation,
force Half Duplex operation, and enable either 100 Mbps
or 10 Mbps operation. All of these modes can be
configured by either asserting the appropriate hardware
pins or by setting the appropriate bits in the MI serial port
Control register.
4.8.2 Clocks
Normally, transmit data sent over the MII/RMII/FBI is
clocked into the 84225 by the rising edge of the output
clock TXCLK. It may be desireable or necessary in some
repeater applications to clock in transmit data from a
master clock from the repeater core. This would require
that transmit data be clocked in on the edge of an input
clock. An input clock is available for clocking in data on
TXD by the rising edge on the CLKIN pin. Notice from the
timing diagrams that CLKIN generates TXCLK, and TXD
data is clocked in on TXCLK edges. This means that TXD
data is also clocked in on the CLKIN edge as well. Thus,
an external clock driving the CLKIN input can also be
used as the clock for TXD.
4.9 SERIAL PORT
4.9.1 General
The 84225 has a MI serial port to set all of the devices's
configuration inputs and read out the status outputs. Any
external device that has an IEEE 802.3 compliant MI
interface can connect directly to the 84225 without any
glue logic, as shown in Figure 12 and Figure 13.
As described earlier, the MI serial port consists of five
lines: MDC, MDIO, and PHYAD[4:2]. However, only 2
lines, MDC and MDIO, are needed to shift data in and out.
PHYAD[4:2] define the three most significant bits of the
PHY address, as described in the Section 4.9.3, Serial
Port Addressing Section.
4.9.2 Polling vs. Interrupt
The status output bits can be monitored by either polling
the serial port or with the interrupt output.
If polling is used, the registers can be read at regular
intervals and the status bits can be checked against their
previous values to determine any changes. To make
polling simpler, all the registers can be accessed in a
single read or write cycle by setting the register address
bits REGAD[4:0] to 11111 and adding enough clocks to
read out all the bits, provided the multiple register access
feature has been enabled.
4.9.3 Serial Port Addressing
The device address for the MI serial port is selected by
connecting the PHYAD[4:2] pins to the desired value. The
PHYAD[1:0] addresses are internally hardwired for each
channel as shown in both Tables 5 and 7.
4.10 UNMANAGED PORT CONFIGURATION
The 84225 has configuration inputs which can “over-ride”
the default configuration state obtained on POWER-UP or
RESET of the device. Use of these pins ANEG,
SPEED_[3:0], and DPLX_[3:0] allow selection of Global
Autonegotiation, Individual Port Speed (10/100), and
Individual Port Duplex (Full/Half), by properly strapping
these pins to VDD or VSS as shown in Table 23. Note
that these pins SHOULD NOT FLOAT but must be
connected either High or Low for proper operation.
In order to obtain the “Default Mode of Operation”, ie:
Auto-negotiation enabled, 100MBs, and Half Duplex; the
ANEG, SPEED_[3:0], and DPLX_[3:0] pins should be set
to 1,1,0 respectively.
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