參數(shù)資料
型號(hào)： 84225
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁數(shù)： 29/86頁
文件大?。?/td> 1297K
代理商： 84225
MD400183/A
29
84225
The internal CRS loopback can be disabled by setting the
TXEN to CRS loopback disable bit in the MI serial port
Channel Configuration register. When this bit is set, TXEN
is no longer looped back to CRS.
2.19.2 Diagnostic Loopback
A diagnostic loopback mode can also be selected by
setting the loopback bit in the MI serial port Control
register. When diagnostic loopback is enabled, TXD[3:0]
data is looped back onto RXD[3:0], TXEN is looped back
onto CRS, RXDV operates normally, the TP receive and
transmit paths are disabled, the transmit link pulses are
halted, and the Half/Full Duplex modes do not change.
Diagnostic loopback mode can not be enabled when the
FBI interface is selected.
2.20 RESET
The 84225 is reset when either:
(1) VDD is applied to the device,
(2) the reset bit is set in the MI serial port Control
register, or
(3) the RESET pin is asserted active low.
When the reset is initiated by either (1) or (2), an internal
power-on reset pulse is generated which resets all internal
circuits, forces the MI serial port bits to their default values,
and latches in new values for the MI address. After the
power-on reset pulse has finished, the reset bit in the MI
serial port Control register is cleared and the device is
ready for normal operation. The device is guaranteed to be
ready for normal operation 50 mS after the reset was
initiated.
When the reset is initiated by (3), the identical procedure
takes place as in (1) and (2), except the device stays in
reset until the RESET pin is deasserted high.
2.21 POWERDOWN
The 84225 can be powered down by setting the
powerdown bit in the MI serial port Control register. In
powerdown mode, the TP outputs are in high impedance
state, all functions are disabled except the MI serial port,
and the power consumption is reduced to a minimum. The
device will be ready for normal operation 50 mS after
powerdown is deasserted.
2.22 CLOCK
The 84225 requires a 25 MHz reference frequency for
internal signal generation in MII mode, and 50 MHz in
RMII mode. This reference frequency must be applied to
the CLKIN pin.
2.23 LED DRIVERS
The LED[3:0] outputs can drive LED’s tied to either VDD
or GND. The LED definitions assume that the LED
outputs are active low. If the LED Anodes are tied to the
positive power supply (through limiting resistors), the LED
will indicate the event as shown in Table 3. If the LED
Cathodes are tied to ground and the Anodes to the 84225
Driver
output,
they
will
complementary events.
indicate
the
respective
The LED[3:0] outputs can also drive other digital inputs.
Table 3. LED Function Definition
Notes:
When the FX interface is enabled, LED0 becomes FEF.
Default = 000 When pin LEDDEF = 0
Bits 16. [13:11] forced to 001 When
pin LEDDEF = 1
Table 4. LED Event Definition
LEDDEF
1
LED3
LINK +
ACT
LINK
100
LED2
COL
LED1
FDX
LED0
10/100
0
ACT
FDX
LINK10
Symbol
ACT
Definition
Activity Occurred, Stretch Pulse to
100 mS
Collision Occurred, Stretch Pulse to
100 mS
100 Mb Link Detected
10 Mb Link Detected
100 Mb or 10 Mb Link Detected
LED on if Link Detected (10 or 100).
LED Blinks if Activity Determined,
Stretch Pulse to 100 mS
Full Duplex Mode Detected with Link
Pass
10 Mb Mode Enabled (High) or
100 Mb Mode Enabled (Low) with
Link Pass
COL
LINK100
LINK10
LINK
LINK+ACT
FDX
10/100
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