參數(shù)資料
型號(hào)： 84225
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁(yè)數(shù)： 9/86頁(yè)
文件大?。?/td> 1297K
代理商： 84225
MD400183/A
9
84225
1.0 PIN DESCRIPTION
118
CLKIN
I
Clock Input.
In MII mode, there must be a 25 MHz clock input to this pin.
In RMII mode, there must be a 50 MHz clock input to this pin. TXCLK is
generated from the input to this pin.
109
RESET
I
Pullup
Hardware Reset Input.
1 = Normal
0 = Device In Reset State
(Reset is complete 50 ms after RESET goes high).
Table 1. AutoNegotiation, Speed & Duplex Mode Combinations
Input Pins
Mode Selected
Aneg
Speed[3:0]
Duplx [3:0]
Auto-
neg
Forced
Modes
[Note 2]
Advertised
Capabilities
Speed
DPLX
Speed
DPLX
0
0000
0000
Off
10
Half
na
na
0
0000
1111
Off
10
Full
na
na
0
1111
0000
Off
100
Half
na
na
0
1111
1111
Off
100
Full
na
na
1
0000
0000
On
na
na
10
Half
1
0000
1111
On
na
na
10
Half/Full
1
1111
0000
On
na
na
10/100
Half/Full
[3]
1
1111
1111
On
na
na
10/100
Half
Note 1: The single ANEG pin applies to all four channels. The four Speed and DPLX apply to each individual channel.
The pins above are shown for all four channels, but each channel can be individually configured for SPEED and DPLX by
appropriately setting the pin for that channel.
Note 2: Forced Modes assume that registers 0 and 4 are at default values.
Note 3: the 84225 can be either controlled through the software or through the hardware. If the device needs to be con-
trolled through the software (Registers 0 to 4), then these seven pins (ANEG, Speed[3:0] , Duplx[3:0]) have to be tied to
their default values of 1, 1111, and 0000 respectively.
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