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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 55/86頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | 84225 |
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MD400183/A
55
84225
Table 23. Hardware Configuration
4.13 LONG CABLE
IEEE 802.3 specifies that 10BaseT and 100BaseTX
operate over twisted pair cable lengths from 0 to 100
meters. The squelch levels can be reduced by 4.5 dB if
the receive level adjust bit is appropriately set in the MI
serial port Channel Configuration register, which will allow
the 84225 to operate with up to 150 meters of twisted pair
cable. The equalizer is already designed to accomodate
between 0 to 150 meters of cable.
4.14 CLOCK
The 84225 requires a 25 MHz reference frequency for
internal signal generation in MII mode, and 50 MHz in
RMII mode. The appropriate reference frequency must
be applied to the CLKIN pin.
4.15 LED DRIVERS
The LED[3:0] outputs can all drive LED’s tied to VDD as
shown in Figure 12 and Figure 13. In addition, the
LED[3:0] outputs can drive LED’s tied to GND as well.
The LED definitions assume that the LED outputs are tied
to VDD, active low signals (otherwise the LED outputs will
indicate their respective opposite events.)
The LEDDEF pin determines the default settings for
LED[3:0]. If LEDDEF = 0, the default functions for
LED[3:0] are Link 100, Activity, Full Duplex, and Link 10,
respectively. If LEDDEF = 1, the LED functions for
LED[3:0] are forced to LINK + ACTIVITY Collision, Full
Duplex and 10/100 Mbps operation, respectively. Table 5
defines the LED functions. Table 4 defines the LED
events.
The LED[3:0] outputs can also drive other digital inputs.
Thus, LED[3:0] can also be used as digital outputs whose
function can be user defined and controlled through the
MI serial port.5V Compatible I/O Operation.
4.16 5V COMPATIBLE I/O OPERATION
The input and output pins of the 84225 are tolerant of
signal levels up to a maximum of 5.5V (including
overshoot etc.). This allows the transceiver to be
operated with 5V controllers that have TTL I/O
characteristics (0.8 to 2.0V Input levels) without the use of
levelshifters or other interfaces.
Controllers and other system components may be
operate with 5V supplies and all inter-chip signals may be
connected directly to the 84225. All required external
logic levels must retain TTL compatability since the 84225
outputs are not guaranteed to achieve higher than 2.3V
with a load of 10ma. However, the inputs of the 84225 will
tolearte TTL or CMOS logic levels being driven into the
device.
This should make replacement of the Physical Layer
transceivers in existing designs quite simple since any 5V
devices do not need to be changed.
4.17 POWER SUPPLY DECOUPLING
There are 18 VDD's and 19 GND's on the 84225.
All VDD's on each individual side should be connected
together (grouped) and tied to a power plane, as close as
possible to the 84225 supply pins. If the VDD's vary in
potential by even a small amount, noise and latchup can
result. The 84225 VDD pins should be kept to within 50
mV of each other.
All GND's should be connected as close as possible to
the device with a large ground plane. If the GND's vary in
potential by even a small amount, noise and latchup can
result. The GND pins should be kept to within 50 mV of
each other.
A 0.01-0.1uF decoupling capacitor should be connected
between the VDD group and GND on each of the 4 sides
of the 84225 as close as possible to the device pins,
preferably within 0.5 in. The value should be chosen
depending on whether the noise from VDD-GND is high
or low frequency. A conservative approach would be to
Configuration
State
Auto-
Negotiate
Speed
Duplex
Normal
(POC/RESET)
Config Pins
Enabled
Advertise
10/100
SPEED_
[3:0]=1
10MBs
Advertise
Full/Half
DPLX_
[3:0]=0
Full
ANEG=1
Complement
State
Config Pins
Disabled
ANEG=0
SPEED_
[3:0]=0
DPLX_
[3:0]=1
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