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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 15/86頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | 84225 |
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MD400183/A
15
84225
normal data nibble that was clocked in on the TXD[3:0]
nibble at the same time as the TXER assertion. The error
nibble is the /H/ symbol, as defined in IEEE 802.3 and
shown in “Table 1. 4B/5B Symbol Mapping,”.
Since CLKIN (input clock) generates TXCLK (output
clock), TXD[3:0], TXEN, and TXER are also clocked in on
the rising edges of CLKIN.
On the receive side, as long as a valid data packet is not
detected, CRS and RXDV are deasserted and RXD[3:0] is
held low. When the start of packet is detected, CRS is
asserted on the falling edge of RXCLK. The assertion of
RXDV indicates that valid data is available on RXD[3:0].
Data may be externally latched using the rising edge of
RXCLK. The RXD[3:0] data has the same frame structure
as the TXD[3:0] data, specified in IEEE 802.3 and shown
in Figure 3. When the end of packet is detected, CRS and
RXDV are deasserted, and RXD[3:0] is held low. CRS and
RXDV also stay deasserted if the channel is in Link Fail
state.
RXER is a receive error output that is asserted when
certain errors are detected on a data nibble. RXER is
asserted on the falling edge of RXCLK for the duration of
the RXCLK clock cycle during which the nibble containing
the error is output on RXD[3:0].
The collision output, COL, is asserted whenever the
collision condition is detected.
2.2.3 MII - 10Mbps
10 Mbps operation is identical to the 100 Mbps operation,
except:
TXCLK and RXCLK clock frequency is 2.5 MHz.
TXER is ignored.
RXER is disabled and always held low.
Receive operation is modified as follows. On the receive
side, when the squelch circuit determines that invalid
data is present on the TP (Twisted Pair) inputs, the
receiver is idle. During idle, RXCLK follows TXCLK,
RXD[3:0] is held low, and CRS and RXDV are
deasserted. When a start of packet is detected on the
TP receive inputs, CRS is asserted and the clock
recovery process starts on the incoming TP input data.
After the receive clock has been recovered from the
data, the RXCLK is switched over to the recovered clock
output and the data valid signal RXDV is asserted on a
falling edge of RXCLK. Once RXDV is asserted, valid
data is clocked out on RXD[3:0] on falling edges of the
RXCLK clock. The RXD[3:0] data has the same packet
structure as the TXD[3:0] data and is formatted as
specified in IEEE 802.3 and shown in Figure 3. When
the end of packet is detected, CRS and RXDV are
deasserted. CRS and RXDV also stay deasserted as
long as the channel is in the Link Fail State.
2.2.4 RMII - 100 Mbps
The RMII is a reduced pin count version of the MII
defined by an industry group, the RMII Consortium. The
RMII is a two-bit wide packet data interface that operates
at 50 Mhz. The 84225 meets all the RMII requirements
outlined in the RMII Consortium specifications and can
directly connect to any Ethernet controller that also
complies with the RMII specifications.
The RMII is similar to the MII, except:
The data path is two bits wide instead of four.
Transmit and receive data is passed over TXD[1:0] and
RXD[1:0] pins, respectively.
The CLKIN clock frequency must be 50 MHz instead
of 25 MHz.
All timing for both transmit and receive is referenced to a
single clock on CLKIN instead of TXCLK for transmit and
RXCLK for receive.
An elastic buffer is present in the receive data path to
account for any difference between the CLKIN and
receive data frequencies. The elastic buffer is 32 bits in
length. Input data from the receiver fills the buffer to a
predetermined threshold level before data is passed to
the RMII outputs. This threshold level can be configured
to either 4 bits or 16 bits by appropriately setting the
RMII threshold select bit in the MI serial port Global
Configuration register.
The MII RXDV and CRS inputs are combined into one
signal that is outputted on the CRS pin. CRS is asserted
active high when incoming packet data is detected on
the receive inputs, stays asserted high until packet data
is no longer detected, and toggles at a 25 MHz rate (low
for irst di-bit of MII nibble, high for second, etc.) from the
end of the packet data detection until end of valid data
transfer from the elastic buffer. During this toggling
interval, valid data is still being output on RXD[1:0].
CRS is inally deasserted when all data has been output
from the internal elastic buffer on RXD[1:0].
RXD[1:0]=00 from start of CRS until valid data is ready
to be output.
TXEN to CRS loopback is disabled.
Any packet that contains an error will assert RXER and
substitute RXD[1:0]=10 for all the data bits from the
error detect point until the end of packet.
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