參數(shù)資料
型號(hào)： 84225
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁(yè)數(shù)： 32/86頁(yè)
文件大?。?/td> 1297K
代理商： 84225
32
MD400183/A
84225
whenever they make a transition or change value, and
they stay latched until they are read. After R/LT bits are
read, they are updated to their current value. The R/LT bits
can also be programmed to assert the interrupt function
as described in the Interrupt section.
Table 6. MI Register Bit Type Definition
Symbol
Name
Definition
Write Cycle
Input
Read Cycle
No Operation,
Hi Z
W
Write
R
Read
No Operation, Hi
Z
Output
R/W
Read/Write
Input
Output
R/
WSC
Read/
Write
Self Clear-
ing
Input
Clears Itself
After Opera-
tion Com-
pleted
Output
R/LL
Read/
Latching
Low
No Operation,
Hi Z
Output
When Bit Goes
Low,
Bit Latched.
When Bit Is
Read, Bit
Updated.
R/LH
Read/
Latching
High
No Operation,
Hi Z
Output
When Bit Goes
High,
Bit Latched.
When Bit Is
Read, Bit
Updated.
R/LT Read/
Latching
on Transi-
tion
No Operation,
Hi Z
Output
When Bit
Transitions,
Bit Latched And
Interrupt Set
When Bit Is
Read, Interrupt
Cleared And Bit
Updated.
2.25.5 Frame Structure
The structure of the serial port frame is shown in Table 7
and a timing diagram is shown in Figure 10. Each serial
port access cycle consists of 32 bits (or 720 bits if multiple
register access is enabled and REGAD[4:0]=11111),
exclusive of idle. The first 16 bits of the serial port cycle
are always write bits and are used for addressing. The last
16/704 bits are from one/all of the 4 x 11 data registers.
The first 2 bits in Table 7 and Figure 10 are start bits and
need to be written as a 01 for the serial port cycle to
continue. The next 2 bits are read and write bits which
determine whether the accessed data register bits will be
read or write. The next 5 bits are device addresses. The 3
most significant bits must match the values on pins
PHYAD[4:2] and the 2 least significant bits select one of
four channels for access. The next 5 bits are register
address select bits which select one of the eleven
registers for access. The next 2 bits are turnaround bits
which are not an actual register bits but extra time to
switch MDIO from write to read if necessary. The final 16
bits of the MI serial port cycle (or 704 bits if multiple
register access is enabled and REGAD[4:0]=11111) come
from the specific data register designated by the register
address bits REGAD[4:0].
2.25.6 Register Structure
The 84225 has eleven 16 bit registers for each channel.
All eleven registers are available for setting configuration
inputs and reading status outputs. A map of the registers
is shown in Table 8. The eleven registers consist of six
registers that are defined by IEEE 802.3 specifications
(Registers 0-5) and five registers that are unique to the
84225 (Registers 16-20).
The structure and bit definition of the Control Register is
shown in Table 9. This register stores various
configuration inputs and its bit definition complies with the
IEEE 802.3 specifications.
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