參數(shù)資料
型號(hào)： AD9548BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 20/112頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
Data Sheet
AD9548
Rev. E | Page 15 of 112
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVDD
SCLK/SCL
SDIO
SDO
DVDD
DVDD3
TCLK
TMS
TDO
TDI
DVDD
RESET
DVDD
NC
17
VSS
18
DACOUTP
19
DACOUTN
20
VSS
23
24
25
26
27
28
29
30
31
32
33
34
36
37
35
38
39
40
41
58
57
56
55
54
53
52
51
50
49
48
47
46
45
59
60
61
62
63
64
65
66
78
77
76
75
74
73
72
71
70
69
68
67
79
80
81
82
83
84
85
86
87
88
AD9548
TOP VIEW
(Not to Scale)
21
AVDD3
22
AVDD3
42
43
44
NC
AVDD
TDC_VRT
TDC_VRB
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).
REFB
REFBB
SYSCLK_VREG
AVDD3
AVDD
SYSCLKN
SYSCLKP
VSS
REFA
REFAA
AVDD
AVDD3
M7
M6
M5
M4
DV
DD
DV
DD3
AV
DD
AV
DD
DV
DD
IRQ
NC
AV
DD3
RE
F
DD
RE
F
CC
RE
F
C
RE
F
D
M3
M2
M1
M0
AVDD3
SYSCLK_LF
NC
88-LEAD LFCSP
12mm × 12mm
0.5mm PITCH
AV
DD3
DV
DD
AV
DD
VSS
CL
KI
NN
CL
KI
NP
VSS
AV
DD
AV
DD3
AV
DD
AV
DD
O
UT
1P
O
UT
1N
AV
DD3
O
UT
2P
O
UT
3P
O
UT
3N
O
UT
2N
O
UT
_RS
E
T
AV
DD3
O
UT
0P
O
UT
0N
AV
DD3
AV
DD
08022-
002
CS/SDA
Figure 2. 88-Lead LFCSP Pin Configuration
Table 21. Pin Function Descriptions
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
1, 6, 12, 77,
83, 88
DVDD
I
Power
1.8 V Digital Supply.
2
SCLK/SCL
I
3.3 V CMOS
Serial Programming Clock. Data clock for serial programming.
3
SDIO
I/O
3.3 V CMOS
Serial Data Input/Output. When the device is in 4-wire mode, data is written via
this pin. In 3-wire mode, both data reads and writes occur on this pin. There is no
internal pull-up/pull-down resistor on this pin.
4
SDO
O
3.3 V CMOS
Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in
3-wire mode). There is no internal pull-up/pull-down resistor on this pin.
5
CS/SDA
I
3.3 V CMOS
Chip Select (SPI). Active low. When programming a device, this pin must be held
low. In systems where more than one AD9548 is present, this pin enables
individual programming of each AD9548 (in I2C mode, this is a serial data pin).
This pin has an internal 10 k pull-up resistor but only in SPI mode.
7, 82
DVDD3
I
Power
3.3 V I/O Digital Supply.
8
TCLK
I
JTAG Clock. Internal pull-down resistor; no connection if JTAG is not used.
9
TMS
I
JTAG Mode. Internal pull-up resistor; no connection if JTAG is not used.
10
TDO
O
JTAG Output. No connection if JTAG is not used
11
TDI
I
JTAG Input. Internal pull-up resistor; no connection if JTAG is not used.
13
RESET
I
3.3 V CMOS
Chip Reset. When this active high pin is asserted, the chip goes into reset.
This pin has an internal 50 k pull-down resistor.
14, 15
DVDD
I
Power
1.8 V DAC Decode Digital Supply. Keep isolated from the 1.8 V core digital supply.
16, 45, 46
NC
No Connect.
17, 20, 25,
28, 51, 54
VSS
O
Ground
Analog Ground. Connect to ground.
18
DACOUTP
O
Differential
output
DAC Output. DACOUTP contains an internal 50 pull-down resistor.
19
DACOUTN
O
Differential
output
Complementary DAC Output. DACOUTN contains an internal 50 pull-down
resistor.
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