參數(shù)資料
型號： AD9548BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 54/112頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
AD9548
Data Sheet
Rev. E | Page 46 of 112
Typically, when the AD9548 asserts the IRQ pin, the user
interrogates the IRQ monitor register to identify the source of
the interrupt request. After servicing an indicated interrupt, the
user should clear the associated IRQ monitor register bit via the
IRQ clearing register (Address 0x0A04 to Address 0x0A0B).
The bits in the IRQ clearing register have a one-to-one
correspondence with the bits in the IRQ monitor register. Note
that the IRQ clearing register is autoclearing. The IRQ pin
remains asserted until the user clears all of the bits in the IRQ
monitor register that indicate an interrupt.
It is also possible to collectively clear all of the IRQ monitor
register bits by setting the reset all IRQs bit in the reset function
register (Register 0x0A03, Bit 1). Note that this is an
autoclearing bit. Setting this bit results in deassertion of the IRQ
pin. Alternatively, the user can program any of the
multifunction pins to clear all IRQs. This allows the user to
clear all IRQs by means of a hardware pin rather than by a serial
I/O port operation.
Note that the IRQ function detects a state change in the function
that is being monitored. However, if IRQs are cleared (or if they
are enabled for the first time), an IRQ will not be generated for
a pre-existing condition. The state must change after the IRQ is
enabled. For example, if REFA is already invalid before a "REFA
invalid" IRQ is enabled, an IRQ will not be generated.
WATCHDOG TIMER
The watchdog timer is a general-purpose programmable timer.
To set the timeout period, the user writes to the 16-bit
watchdog timer register (Address 0x0211 to Address 0x0212). A
value of 0 in this register disables the timer. A nonzero value
sets the timeout period in milliseconds, giving the watchdog
timer a range of 1 ms to 65.535 sec. The relative accuracy of the
timer is approximately 0.1% with an uncertainty of 0.5 ms.
If enabled, the timer runs continuously and generates a timeout
event whenever the timeout period expires. The user has access
to the watchdog timer status via the IRQ mechanism and the
multifunction pins (M0 to M7). In the case of the multifunction
pins, the timeout event of the watchdog timer is a pulse that
lasts 32 system clock periods.
There are two ways to reset the watchdog timer (thereby
preventing it from causing a timeout event). The first is by
writing a Logic 1 to the autoclearing reset watchdog bit in the
reset function register (Register 0x0A03, Bit 0). Alternatively,
the user can program any of the multifunction pins to reset the
watchdog timer. This allows the user to reset the timer by
means of a hardware pin rather than by a serial I/O port operation.
EEPROM
EEPROM Overview
The AD9548 contains an integrated 2048-byte, electrically
erasable, programmable read-only memory (EEPROM). The
AD9548 can be configured to perform a download at power-up
via the multifunction pins (M3 to M7), but uploads and down-
loads can also be done on demand via the EEPROM control
register (Address 0x0E00 to Address 0x0E03).
The EEPROM provides the ability to upload and download
configuration settings to and from the register map. Figure 50
shows a functional diagram of the EEPROM.
Register 0x0E10 to Register 0x0E3F represent a 48-byte scratch
pad that enables the user to store a sequence of instructions for
transferring data to the EEPROM from the device settings
portion of the register map. Note that the default values for
these registers provide a sample sequence for saving/retrieving
all of the AD9548 EEPROM-accessible registers. Figure 50
shows the connectivity between the EEPROM and the controller
that manages data transfer between the EEPROM and the
register map.
The controller oversees the process of transferring EEPROM data
to and from the register map. There are two modes of operation
handled by the controller: saving data to the EEPROM (upload
mode) or retrieving data from the EEPROM (download mode).
In either case, the controller relies on a specific instruction set.
EEPROM
(000 TO 7FF)
DAT
A
DAT
A
DATA
EEPROM
ADDRESS
POINTER
M7
M6
M5
M4
M3
REGISTER MAP
DEVICE SETTINGS
(0100 TO 0A10)
SCRATCH PAD
(0E10 TO 0E3F)
SERIAL
INPUT/OUTPUT
PORT
C
O
N
D
IT
IO
N
(0
E0
1
[4
:0
])
SCRATCH PAD
ADDRESS
POINTER
DEVICE
SETTINGS
ADDRESS
POINTER
EEPROM
CONTROLLER
080
22-
02
4
Figure 50. EEPROM Functional Diagram
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