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參數(shù)資料
型號: AD9548BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 23/112頁
文件大?。?/td> 0K
描述: IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告: AD9548 Mask Change 20/Oct/2010
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750kHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 88-VFQFN 裸露焊盤,CSP
供應商設備封裝: 88-LFCSP-VQ(12x12)
包裝: 托盤
AD9548
Data Sheet
Rev. E | Page 18 of 112
TYPICAL PERFORMANCE CHARACTERISTICS
fR = input reference clock frequency; fO = clock frequency; fSYS = SYSCLK input frequency; fS = internal system clock frequency; LBW = DPLL
loop bandwidth; PLL off = SYSCLK PLL bypassed; PLL on = SYSCLK PLL enabled; ICP = SYSCLK PLL charge pump current; LF = SYSCLK
PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, fS = 1 GHz, ICP = automatic mode, LF = internal, unless otherwise noted.
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
100
1k
10k
100k
1M
10M
100M
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 173fs (–75.4dBc)
20kHz TO 80MHz: 315fs (–70.2dBc) (EXTRAPOLATED)
08022-
068
Figure 3. Additive Phase Noise (Output Driver = LVPECL),
fR = 19.44 MHz, fO = 155.52 MHz,
LBW = 1 kHz, fSYS = 1 GHz, PLL Off
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
100
1k
10k
100k
1M
10M
100M
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 333fs (–69.8dBc)
20kHz TO 80MHz: 430fs (–67.6dBc) (EXTRAPOLATED)
08022-
056
Figure 4. Additive Phase Noise (Output Driver = LVPECL),
fR = 19.44 MHz, fO = 155.52 MHz,
LBW = 1 kHz, fSYS = 50 MHz (Crystal), PLL On
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
100
1k
10k
100k
1M
10M
100M
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 103fs (–74.0dBc)
20kHz TO 80MHz: 160fs (–70.1dBc)
08022-
066
Figure 5. Additive Phase Noise (Output Driver = LVPECL),
fR = 19.44 MHz, fO = 311.04 MHz,
LBW = 1 kHz, fSYS = 1 GHz, PLL Off
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
100
1k
10k
100k
1M
10M
100M
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 310fs (–64.4dBc)
20kHz TO 80MHz: 330fs (–63.9dBc)
08022-
067
Figure 6. Additive Phase Noise (Output Driver = LVPECL),
fR = 19.44 MHz, fO = 311.04 MHz,
LBW = 1 kHz, fSYS = 50 MHz (Crystal), PLL On
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