參數(shù)資料
型號(hào)： AD9548BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 44/112頁(yè)
文件大小： 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
Data Sheet
AD9548
Rev. E | Page 37 of 112
Switchover
Switchover occurs when the loop controller switches directly
from one input reference to another. Functionally, the AD9548
handles a reference switchover by briefly entering holdover
mode and then immediately recovering. During the switchover
event, however, the AD9548 preserves the status of the lock
detectors to avoid phantom unlock indications.
Holdover
The holdover state of the DPLL is an open-loop operating mode.
That is, the device no longer operates as a closed-loop system.
Instead, the output frequency remains constant and is dependent
on the device programming and availability of tuning word history.
If a tuning word history exists (see the Frequency Tuning Word
History section), then the holdover frequency is the average
frequency just prior to entering the holdover state. If there is no
tuning word history, then the holdover frequency depends on
the state of the single sample fallback bit in the history mode
register (Register 0x031B, Bit 4). If the single sample fallback bit
is Logic 0, then the holdover frequency is the frequency defined
in the free running frequency tuning word register (Address
0x0300 to Address 0x0305). If the single sample fallback bit is
Logic 1, then the holdover frequency is the last instantaneous
frequency output by the DDS just prior to the device entering
holdover mode (note that this is not the average frequency prior
to holdover).
The initial holdover frequency accuracy depends on the loop
bandwidth of the DPLL and the time elapsed to compute a tuning
word history. The longer the historical average, the more accurate
the initial holdover frequency (assuming a drift-free system clock).
Furthermore, the stability of the system clock establishes the
stability and long-term accuracy of the holdover output frequency.
Another consideration is the 48-bit frequency tuning resolution
of the DDS and its relationship to fractional frequency error,
fO/fO, as follows:
O
S
O
f
49
2
=
where, fS is the sample rate of the output DAC, and fO is the DDS
output frequency.
The worst-case scenario is maximum fS (1 GHz) and minimum fO
(62.5 MHz), which yields fO/fO = 2.8 × 1014, less than one part
in 10 trillion.
Recovery from Holdover
When in holdover and a valid reference becomes available, the
device exits holdover operation. The loop state machine restores
the DPLL to closed-loop operation, locks to the selected reference,
and sequences the recovery of all the loop parameters based on
the profile settings for the active reference.
Note that, if the user holdover bit (Register 0x0A01, Bit 6) is set,
the device does not automatically exit holdover when a valid
reference is available. However, automatic recovery can occur
after clearing the user holdover bit.
SYSTEM CLOCK INPUTS
Functional Description
The system clock circuit provides a low jitter, stable, high frequency
clock for use by the rest of the chip. The user has the option of
directly driving the SYSCLKx inputs with a high frequency
clock source at the desired system clock rate. Alternatively, the
SYSCLKx input can be configured to operate in conjunction
with the internal SYSCLK PLL. The SYSCLK PLL can synthesize
the system clock by means of a crystal resonator connected
across the SYSCLKx input pins or by means of direct application
of a low frequency clock source.
The SYSCLKx inputs are internally biased to a dc level of ~1 V. Take
care to ensure that any external connections do not disturb the dc
bias because this may significantly degrade performance. Generally,
the recommendation is that the SYSCLKx inputs be ac-coupled
to the signal source (except when using a crystal resonator).
Low Loop Bandwidth Applications Using a TCXO/OCXO
For many applications, the use of a crystal oscillator is a cost-
effective and simple choice. The stability is good enough to support
loop bandwidths down to 50 Hz, and the holdover performance
is good enough for all except the most demanding applications.
In cases where Stratum 2 or Stratum 3 holdover performance is
needed, or in cases where the loop bandwidth must be <50 Hz,
either a TCXO or OCXO must be used. If the loop bandwidths
are lower than 10 mHz, an OCXO must be used. Choose a
TCXO/OCXO with a high output frequency and CMOS output
to achieve the best performance. The AN-1079 Application Note,
Determining the Maximum Tolerable Frequency Drift Rate of the
AD9548 System Clock in Low Loop Bandwidth Applications,
discusses system clock performance considerations for low loop
bandwidth applications.
When interfacing the TCXO/OCXO, a voltage divider on the
output should be used to reduce the voltage swing to 1 V p-p,
and that signal should be ac-coupled to the SYSCLKP pin. The
SYSCLKN pin can be bypassed to ground with a 0.01 F capacitor.
Choosing the System Clock Oscillator Frequency
The best performance of the AD9548 is achieved when the system
clock is not an integer multiple of the DDS output frequency.
As an example, using a 19.44 MHz oscillator for the system clock in
a 156.25 MHz Ethernet application yields better performance than
a 25 MHz oscillator.
Another good system clock choice for many communications
applications is a 49.152 MHz crystal used in IEEE 1394 (FireWire)
because nearly all output frequencies are not integer related to this
frequency, and the crystal is readily available.
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