參數(shù)資料
型號： AD9548BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 45/112頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標準包裝： 1
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應商設備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
AD9548
Data Sheet
Rev. E | Page 38 of 112
2×
÷N
VCO
CALIBRATION
LOCK
DETECT
SYSTEM
CLOCK
÷M
LOOP
FILTER
SYSCLKN
SYSCLKP
SYSCLK_VREG
SYSCLK_LF
HF
XTAL
LF
48
52
53
49
PFD
AND
CHARGE
PUMP
08022
-020
Figure 46. System Clock Block Diagram
System Clock Details
A block diagram of the system clock appears in Figure 46. The
signal at the SYSCLKx input pins becomes the internally buffered
DAC sampling clock (fS) via one of three paths.
High frequency direct (HF)
Low frequency synthesized (LF)
Crystal resonator synthesized (XTAL)
Note that both the LF and XTAL paths require the use of the
SYSCLK PLL (see the SYSCLK PLL Multiplier section).
The main purpose of the HF path is to allow the direct use of a high
frequency (500 MHz to 1 GHz) external clock source for clocking
the AD9548. This path is optimized for high frequency and low
noise floor. Note that the HF input also provides a path to SYSCLK
PLL (see the SYSCLK PLL Multiplier section), which includes
an input divider (M) programmable for divide-by -1, -2, -4, or -8.
The purpose of the divider is to limit the frequency at the input
to the PLL to less than 150 MHz (the maximum PFD rate).
The LF path permits the user to provide an LVPECL, LVDS,
CMOS, or sinusoidal low frequency clock for multiplication by
the integrated SYSCLK PLL. The LF path handles input
frequencies from 3.5 MHz up to 100 MHz. However, when
using a sinusoidal input signal, it is best to use a frequency in
excess of 20 MHz. Otherwise, the resulting low slew rate can
lead to substandard noise performance. Note that the LF path
includes an optional 2× frequency multiplier to double the rate
at the input to the SYSCLK PLL and potentially reduce the PLL
in-band noise. However, to avoid exceeding the maximum PFD
rate of 150 MHz, using the 2× frequency multiplier is valid only
for input frequencies below 125 MHz.
The XTAL path enables the connection of a crystal resonator
(typically 10 MHz to 50 MHz) across the SYSCLKx input pins.
An internal amplifier provides the negative resistance required
to induce oscillation. The internal amplifier expects a 3.2 mm ×
2.5 mm AT cut, fundamental mode crystal with a maximum
motional resistance of 100 Ω. The following crystals, listed in
alphabetical order, may meet these criteria. Note that, whereas
these crystals may meet the preceding criteria according to their
data sheets, Analog Devices, Inc., does not guarantee their
operation with the AD9548 nor does Analog Devices endorse
one crystal manufacturer/supplier over another.
AVX/Kyocera CX3225SB
ECS ECX-32
Epson/Toyocom TSX-3225
Fox FX3225BS
NDK NX3225SA
Siward SX-3225
SYSCLK PLL MULTIPLIER
The SYSCLK PLL multiplier is an integer-N design and relies on
an integrated LC tank and VCO. It provides a means to convert
a low frequency clock input to the desired system clock
frequency, fS (900 MHz to 1 GHz). The SYSCLK PLL multiplier
accepts input signals between 3.5 MHz and 500 MHz, but
frequencies in excess of 150 MHz require the M-divider to
ensure compliance with the maximum PFD rate (150 MHz).
The PLL contains a feedback divider (N) that is programmable
for divide values between 6 and 255. The nominal VCO gain is
70 MHz/V.
Lock Detector
The SYSCLK PLL has a built-in lock detector. Register 0x0100,
Bit 2 determines whether the lock detector is active. When
active (default), the user controls the sensitivity of the lock
detector via the lock detect divider bits (Register 0x0100, Bits[1:0]).
Note that 0 must be written to the system clock stability timer
(Register 0x0106 to Register 0x0108) whenever the lock
detector is disabled (Register 0x0100, Bit 2 = 1).
The SYSCLK PLL phase detector operates at the PFD rate,
which is fVCO/N. Each PFD sample indicates whether the
reference and feedback signals are phase aligned (within a
certain threshold range).
While the PLL is in the process of acquiring a lock condition,
the PFD samples typically consist of an arbitrary sequence of
in-phase and out-of-phase indications. As the PLL approaches
complete phase lock, the number of consecutive in-phase PFD
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