參數(shù)資料
型號(hào)： AD9548BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 43/112頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤(pán)
AD9548
Data Sheet
Rev. E | Page 36 of 112
When the DPLL is in free-run mode, the DDS tuning word is
the value stored in the free running frequency tuning word
register (Address 0x0300 to Address 0x0305). When the DPLL
is operating normally (closed loop), the DDS tuning word
comes from the output of the digital loop filter, which changes
dynamically in order to maintain phase lock with the input
reference signal (assuming that the device has not performed an
automatic switch to holdover mode). When the DPLL is in
holdover mode, the DDS tuning word depends on a historical
record of past tuning words during the time that the DPLL
operated in closed-loop mode.
However, regardless of the operating mode, the DDS output
frequency is ultimately subject to the boundary conditions
imposed by the frequency clamp logic, as explained in the
Frequency Clamp
The user controls the frequency clamp boundaries via the pull-
in range limits registers (Address 0x0307 to Address 0x030C).
These registers allow the user to fix the DDS output frequency
between an upper and lower bound with a granularity of 24 bits.
Note that these upper and lower bounds apply regardless of the
frequency tuning word that appears at the input to the DDS.
The register value relates to the absolute upper or lower
frequency bound (fCLAMP) as
fCLAMP = fS × (N/224)
Where N is the value stored in the upper- or lower-limit
register, and fS is the system sample rate.
Even though the frequency clamp limits put a bound on the
DDS output frequency, the DPLL is still free to steer the DDS
frequency within the clamp limits. The default register values
set the clamp range from 0 Hz (dc) to fS, effectively eliminating
the frequency clamp functionality until the user alters the
register values.
Frequency Tuning Word History
The AD9548 has the ability to track the history of the tuning
word samples generated by the DPLL digital loop filter output.
It does so by periodically computing the average tuning word
value over a user specified interval. The user programs the
interval via the 24-bit history accumulation timer register
(Address 0x0318 to Address 0x031A). This 24-bit value
represents
a time interval (TAVG) in milliseconds that extends from 1 ms to
a maximum of 4:39:37.215 (hr:min:sec).
Note that history accumulation timer = 0 should not be
programmed because it may cause improper device operation.
The control logic performs a calculation of the average tuning
word during the TAVG interval and stores the result in the
holdover history register (Address 0D14 to Address 0D19).
Computation of the average for each TAVG interval is
independent of the previous interval (that is, the average is a
memoryless average as opposed to a true moving average). In
addition, at the end of each TAVG interval, the device generates
an internal strobe pulse. The strobe pulse sets the history
updated bit in the IRQ monitor register (assuming the bit is
enabled via the IRQ mask register). Furthermore, the strobe
pulse is available as an output signal via the multifunction pins
History accumulation begins whenever the device switches to a
new reference. By default, the device clears any previous history
when it switches to a new reference. Furthermore, the user can
clear the tuning word history under software control via
Register 0x0A03, Bit 2, or under hardware control via the
multifunction pins (see the Multifunction Pins (M0 to M7)
section). However, the user has the option of programming the
device to retain (rather than clear) the old history by setting the
persistent history bit (Register 0x031B, Bit 3).
Whenever the tuning word history is nonexistent (that is, after a
power-up, reset, or switchover to a new reference with the
persistent history bit cleared), the device waits for the history
accumulation timer (TAVG) to expire before storing the first
history value in the holdover history register.
In cases where TAVG is quite large (4 hours, for example), a
problem arises in that the first averaged result does not become
available until the full TAVG interval passes. Thus, it is possible
that as much as 4 hours can elapse before the first averaged
result is available. If the device has to switch to holdover mode
during this time, a tuning word history is not available.
To alleviate this problem, the user has access to the incremental
average bits in the history mode register (Register 0x031B,
Bits[2:0]). If the history has been cleared, then this 3-bit value,
K (0 ≤ K ≤ 7), specifies the number of intermediate averages to
take during the first, and only the first, TAVG interval. When
K = 0, no intermediate averages are calculated; therefore, the
first average occurs after interval TAVG (the default operating
mode). However, if K = 4, for example, four intermediate
averages are taken during the first TAVG interval.
These average computations occur at TAVG/16, TAVG/8, TAVG/4,
TAVG/2, and TAVG (notice that the denominator exhibits a
sequence of powers of 2 beginning with TAVG/2K). The calcu-
lation of intermediate averages occurs only during the first
TAVG interval. All subsequent average computations occur at
evenly spaced intervals of TAVG.
LOOP CONTROL STATE MACHINE
The loop control state machine is responsible for monitoring,
initiating, and sequencing changes to the DPLL loop. Generally,
it automatically controls the transition between input references
and the entry and exit of holdover mode. In controlling loop
state changes, the state machine also arbitrates the application
of new loop filter coefficients, divider settings, and phase
detector offsets based on the profile settings. The user can
manually force the device into holdover or free-run mode via
the loop mode register (Address 0x0A01), as well as force the
selection of a specific input reference.
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