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參數(shù)資料
| 型號： | AD9548BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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Data Sheet
AD9548
Rev. E | Page 47 of 112
Table 27. EEPROM Controller Instruction Set
Instruction
Value (Hex)
Instruction Type
Bytes
Required
Description
0x00 to 0x7F
Data
3
A data instruction tells the controller to transfer data to or from the device settings
part of the register map. A data instruction requires two additional bytes that
together indicate a starting address in the register map. Encoded in the data
instruction is the number of bytes to transfer, which is one more than the
instruction value.
0x80
I/O update
1
When the controller encounters this instruction while downloading from the
EEPROM, it issues a soft I/O update (see Register 0x0005 in Table 42).
0xA0
Calibrate
1
When the controller encounters this instruction while downloading from the
EEPROM, it initiates a system clock calibration sequence (see Register 0x0A02
0xA1
Distribution sync
1
When the controller encounters this instruction while downloading from the
EEPROM, it issues a sync pulse to the output distribution synchronization (see
Register 0x0A02 in Table 121).
0xB0 to 0xCF
Condition
1
0xB1 to 0xCF are condition instructions and correspond to Condition 1 through
Condition 31, respectively. 0xB0 is the null condition instruction. See the EEPROM
Conditional Processing section for details.
0xFE
Pause
1
When the controller encounters this instruction in the scratch pad while uploading
to the EEPROM, it resets the scratch pad address pointer and holds the EEPROM
address pointer at its last value. This allows storage of more than one instruction
sequence in the EEPROM. Note that the controller does not copy this instruction to
the EEPROM during upload.
0xFF
End
1
When the controller encounters this instruction in the scratch pad while uploading
to the EEPROM, it resets both the scratch pad address pointer and the EEPROM
address pointer and then enters an idle state.
When the controller encounters this instruction while downloading from the
EEPROM, it resets the EEPROM address pointer and then enters an idle state.
EEPROM Instructions
Table 27 lists the EEPROM controller instruction set. The
controller recognizes all instruction types whether it is in
upload or download mode, except for the pause instruction,
which it only recognizes in upload mode.
The I/O update, calibrate, distribution sync, and end instruct-
tions are mostly self-explanatory. The others, however, warrant
further detail, as described in the following paragraphs.
Data instructions are those that have a value from 0x00 to 0x7F.
A data instruction tells the controller to transfer data between
the EEPROM and the register map. The controller needs the
following two parameters to carry out the data transfer:
The number of bytes to transfer
The register map target address
The controller decodes the number of bytes to transfer directly
from the data instruction itself by adding one to the value of the
instruction. For example, the data instruction, 1A, has a decimal
value of 26; therefore, the controller knows to transfer 27 bytes
(one more than the value of the instruction). Whenever the
controller encounters a data instruction, it knows to read the
next two bytes in the scratch pad because these contain the
register map target address.
Note that, in the EEPROM scratch pad, the two registers that
comprise the address portion of a data instruction have the
MSB of the address in the D7 position of the lower register
address. The bit weight increases left to right, from the lower
register address to the higher register address. Furthermore, the
starting address always indicates the lowest numbered register
map address in the range of bytes to transfer. That is, the
controller always starts at the register map target address and
counts upward regardless of whether the serial I/O port is
operating in I2C, SPI LSB-first, or SPI MSB-first mode.
As part of the data transfer process during an EEPROM upload,
the controller calculates a 1-byte checksum and stores it as the final
byte of the data transfer. As part of the data transfer process during
an EEPROM download, however, the controller again calculates
a 1-byte checksum value but compares the newly calculated
checksum with the one that was stored during the upload process.
If an upload/download checksum pair does not match, the controller
sets the EEPROM fault status bit. If the upload/download checksums
match for all data instructions encountered during a download
sequence, the controller sets the EEPROM complete status bit.
Condition instructions are those that have a value from 0xB0 to
0xCF. Condition instructions 0xB1 to 0xCF represent
Condition 1 to Condition 31, respectively. The 0xB0 condition
instruction is special because it represents the null condition
(see the EEPROM Conditional Processing section).
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| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
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