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參數(shù)資料
| 型號(hào)： | AD9548BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 42/112頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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Data Sheet
AD9548
Rev. E | Page 35 of 112
DAC
(14-BIT)
PHASE
OFFSET
Q
D
fS
FREQUENCY
TUNING WORD
(FTW)
DAC+
DAC–
14
19
48
19
ANGLE TO
AMPLITUDE
CONVERSION
48
48-BIT ACCUMULATOR
16
0
8022
-018
Figure 43. DDS Block Diagram
The input to the DDS is the 48-bit FTW. The FTW serves as a
step size value. On each cycle of fS, the accumulator adds the
value of the FTW to the running total at its output. For
example, given FTW = 5, the accumulator counts by fives,
incrementing on each fS cycle. Over time, the accumulator
reaches the upper end of its capacity (248 in this case), at which
point, it rolls over but retains the excess. The average rate at
which the accumulator rolls over establishes the frequency of
the output sinusoid. The average rollover rate of the accumulator
establishes the output frequency (fDDS) of the DDS and is given by
S
DDS
f
FTW
f
48
2
Solving this equation for FTW yields
S
DDS
f
FTW
48
2
round
For example, given that fS = 1 GHz and fDDS = 155.52 MHz, then
FTW = 43,774,988,378,041 (0x27D028A1DFB9).
Note that the minimum DAC output frequency is 62.5 MHz;
therefore, normal operation requires an FTW that yields an
output frequency in excess of this lower bound.
DDS Phase Offset
The relative phase of the sinusoid generated by the DDS is
numerically controlled by adding a phase offset word to the output
of the DDS accumulator. This is accomplished via the open loop
phase offset register (Address 0x030D to Address 0x030E),
which is a programmable 16-bit value (Δphase). The resulting
phase offset, ΔΦ (in radians), is given by
16
2
Φ
phase
Phase offset and relative time offset are directly related. The
time offset is (phase/216)/fDDS (in seconds), where fDDS is the
output frequency of the DDS (in hertz).
DAC Output
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. The DAC
translates the numeric values to an analog signal. The DAC
output signal appears at two pins that constitute a balanced
current source architecture (see Figure 44).
CURRENT
SWITCH
ARRAY
SWITCH
CONTROL
IFS
ISCALE
AVDD3
DACOUTP
DACOUTN
CURRENT
MIRROR
GND
21
22
GND
18
19
CODE
08
02
2-
0
19
CODE
50
14
10
IFS (1–
)
214 – 1
CODE
IFS (
)
214 – 1
Figure 44. DAC Output Pins
The value of IFS is programmable via the 10-bit DAC full-scale
current word in the DAC current register (Address 0x0213 to
Address 0x0214). The value of the 10-bit word (ISCALE) sets IFS
according to the following formula:
SCALE
I
16
3
72
μA
120
FS
I
TUNING WORD PROCESSING
The frequency tuning words that dictate the output frequency
of the DDS come from one of three sources (see Figure 45).
The free running frequency tuning word register
The output of the digital loop filter
The output of the tuning word history processor
08
02
2-
07
0
TUNING WORD
HISTORY
PROCESSOR
TUNING WORD
HISTORY
FREE-RUN
TUNING WORD
UPDATE
FROM DIGITAL
LOOP FILTER
TO DDS
TUNING
WORD
ROUTING
CONTROL
TUNING
WORD
CLAMP
LOWER
TUNING
WORD
UPPER
TUNING
WORD
Figure 45. Tuning Word Processing
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| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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