參數資料
| 型號： | AD9548BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 7/112頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9548
Data Sheet
Rev. E | Page 104 of 112
Table 148. EEPROM Storage Sequence for Reference Input Settings
Address
Bits
Bit Name
Description
0x0E1F
[7:0]
Reference inputs
The default value of this register is 0x07, which the controller interprets as a data
instruction. Its decimal value is 7, which tells the controller to transfer eight bytes
of data (7 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x07 in the EEPROM and increments the EEPROM address pointer.
0x0E20
[7:0]
Reference inputs
The default value of these two registers is 0x0500. Note that Register 0x0E20 and
Register 0x0E21 are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0500). The controller
stores 0x0500 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers eight bytes from the register map (beginning at Address 0x0500) to the
EEPROM and increments the EEPROM address pointer by nine (eight data bytes
and one checksum byte). The eight bytes transferred correspond to the reference
inputs parameters in the register map.
0x0E21
[7:0]
Table 149. EEPROM Storage Sequence for Profile 0 and Profile 1 Settings
Address
Bits
Bit Name
Description
0x0E22
[7:0]
Profile 0 and Profile 1
The default value of this register is 0x63, which the controller interprets as a data
instruction. Its decimal value is 99, which this tells the controller to transfer 100
bytes of data (99 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x63 in the EEPROM and increments the EEPROM address pointer.
0x0E23
[7:0]
Profile 0 and Profile 1
The default value of these two registers is 0x0600. Note that Register 0x0E23 and
Register 0x0E24 are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0600). The controller
stores 0x0600 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 100 bytes from the register map (beginning at Address 0x0600) to the
EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and
one checksum byte). The 99 bytes transferred correspond to the Profile 0 and
Profile 1 parameters in the register map.
0x0E24
[7:0]
Table 150. EEPROM Storage Sequence for Profile 2 and Profile 3 Settings
Address
Bits
Bit Name
Description
0x0E25
[7:0]
Profile 2 and Profile 3
The default value of this register is 0x63, which the controller interprets as a data
instruction. Its decimal value is 99, which tells the controller to transfer 100 bytes of
data (99 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x63 in the EEPROM and increments the EEPROM address pointer.
0x0E26
[7:0]
Profile 2 and Profile 3
The default value of these two registers is 0x0680. Note that Register 0x0E26 and
Register 0x0E27 are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0680). The controller
stores 0x0680 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 100 bytes from the register map (beginning at Address 0x0680) to the
EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and
one checksum byte). The 99 bytes transferred correspond to the Profile 2 and
Profile 3 parameters in the register map.
0x0E27
[7:0]
相關PDF資料 |
PDF描述 |
|---|---|
| V375C36M150BL3 | CONVERTER MOD DC/DC 36V 150W |
| MAX3676EHJ+ | IC CLOCK RECOVERY 32-TQFP |
| ADN2813ACPZ | IC CLK/DATA REC 1.25GBPS 48LFCSP |
| AD800-52BRZ | IC CLK\DATA RECOVERY PLL 20SOIC |
| SY87700VZH | IC CLK/DATA RECOVERY 3.3V 28SOIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
發(fā)布緊急采購，3分鐘左右您將得到回復。