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參數(shù)資料
| 型號： | AD9548BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 68/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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Data Sheet
AD9548
Rev. E | Page 59 of 112
I/O PROGRAMMING REGISTERS
The register map spans an address range from 0x0000 through
0x0E3F (0 to 3647, decimal). Each address provides access to one
byte (eight bits) of data. Each individual register is identified by its
four-digit hexadecimal address (for example, Register 0x0A10).
In some cases, a group of addresses collectively define a register
(for example, the IRQ mask register consists of Register 0x0209,
Register 0x020A, Register 0x020B, Register 0x020C,
Register 0x020D, Register 0x020E, Register 0x020F, and
Register 0x0210).
In general, when a group of registers defines a control parameter,
the LSB of the value resides in the D0 position of the register
with the lowest address. The bit weight increases right to left,
from the lowest register address to the highest register address.
For example, the default value of the incremental phase lock
offset step size register (Address 0x0314 to Address 0x0315)
is the 16-bit hexadecimal number, 0x03E8 (not 0xE803).
Note that the EEPROM storage sequence registers (Address 0x0E10
to Address 0x0E3F) are an exception to the above convention (see
the EEPROM Instructions section).
BUFFERED/ACTIVE REGISTERS
There are two broad categories of registers in the AD9548,
buffered and active (see Figure 67). Buffered registers are those
that can be written to directly from the serial port. They do not
need an I/O update to apply their contents to the internal device
functions. In contrast, active registers require an I/O update to
transfer data between the buffer registers and the internal device
functions. In operation, the user programs as many buffer
registers as desired and then issues an I/O update. The I/O
update occurs by writing to Register 0x0005, Bit 0 = 1 (or by the
external application of the necessary logic level to one of the
multifunction pins previously programmed as an I/O update
input). The contents of buffer registers connected directly to the
internal device functions affect those functions immediately.
The contents of buffer registers that connect to active registers
do not affect the internal device functions until the I/O update
event occurs.
An S or C in the Opt column of the register map identifies a
register as an active register (otherwise, it is a buffer register).
An S entry means that the I/O update signal to the active register is
synchronized with the serial port clock or with an input signal
driving one of the multifunction pins. On the other hand, a C
entry means that the I/O update signal to the active register is
synchronized with a clock signal derived from the internal
When reading back a register that has both buffered and active
contents, the user can use Register 0x0004, Bit 0 to select
whether to read back the buffer or active contents. Readback of
the active contents occurs when Register 0x0004, Bit 0 = 0, and
readback of the buffer contents occurs when Register 0x0004,
Bit 0= 1. Note that a read-only active register requires an I/O
update before reading its contents.
A
C
T
IVE
C
RE
G
IS
T
E
RS
A
C
T
IVE
S
R
EG
IST
ER
S
I/O
U
P
D
A
TE
TO
IN
TE
R
N
A
L
D
E
V
IC
E
FU
N
C
TION
S
BU
FFE
R
E
G
IS
T
E
R
S
FROM
MULTIFUNCTION
PIN LOGIC
SERIAL
CONTROL
PORT
fS/32
EDGE
DETECT
CS/SDA
SCLK/SCL
SDIO
SDO
5
3
4
2
08022-
041
Figure 67. Buffered and Active Registers
AUTOCLEAR REGISTERS
An A in the Opt column of the register map identifies an autoclear
register. Typically, the active value for an autoclear register takes
effect following an I/O update. The bit is cleared by the internal
device logic upon completion of the prescribed action.
REGISTER ACCESS RESTRICTIONS
Read and write access to the register map may be restricted based
on the register in question, the source and direction of access, and
the current state of the device. Each register can be classified as one
or more access types. When more than one type applies, the most
restrictive condition that applies at the moment is used.
Whenever access is denied to a register, all attempts to read the
register return a 0 byte, and all attempts to write to the register are
ignored. Access to nonexistent registers is handled in the same way
as for a denied register.
Regular Access
Registers with regular access do not fall into any other category.
Both read and write access to registers of this type can be from
either the serial ports or EEPROM controller. Only one of these
sources can have access to a register at any given time (access is
mutually exclusive). When the EEPROM controller is active, either
in load or store mode, it has exclusive access to these registers.
Read-Only Access
An R in the Opt column of the register map identifies read-only
registers. Access is available at all times, including when the
EEPROM controller is active.
Exclusion from EEPROM Access
An E in the Opt column of the register map identifies a register
with contents that are inaccessible to the EEPROM. The contents of
this type of register cannot be transferred directly to the
EEPROM or vice versa. Note that read-only registers (R) are
inaccessible to the EEPROM, as well.
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| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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