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參數(shù)資料
| 型號(hào)： | ADSP-21469KBCZ-4 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 27/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 32/40BIT 450MHZ 324BGA |
| 產(chǎn)品變化通告： | Pin Function Change 08/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART |
| 時(shí)鐘速率： | 450MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 324-CSPBGA |
| 包裝： | 托盤 |
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ADSP-21469
Rev. 0
|
Page 33 of 72
|
June 2010
AMI Read
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 30. Memory Read
Parameter
Min
Max
Unit
Timing Requirements
tDAD
Address, Selects Delay to Data Valid1, 2
W + tDDR2_CLK –5.4
ns
tDRLD
AMI_RD Low to Data Valid1
W – 3.2
ns
tSDS
Data Setup to AMI_RD High
2.5
ns
tHDRH
Data Hold from AMI_RD High3, 4
0ns
tDAAK
AMI_ACK Delay from Address, Selects2, 5
tDDR2_CLK –9.5 + W
ns
tDSAK
AMI_ACK Delay from AMI_RD Low4
W – 7.0
ns
Switching Characteristics
tDRHA
Address Selects Hold After AMI_RD High
RH + 0.20
ns
tDARL
Address Selects to AMI_RD Low2
tDDR2_CLK – 3.8
ns
tRW
AMI_RD Pulse Width
W – 1.4
ns
tRWR
AMI_RD High to AMI_RD Low
HI + tDDR2_CLK – 1
ns
W = (number of wait states specified in AMICTLx register) × tDDR2_CLK.
RHC = (number of Read Hold Cycles specified in AMICTLx register) × tDDR2_CLK
Where PREDIS = 0
HI = RHC: Read to Read from same bank
HI = RHC + IC: Read to Read from different bank
HI = RHC + Max (IC, (4 × tDDR2_CLK)): Read to Write from same or different bank
Where PREDIS = 1
HI = RHC + Max(IC, (4 × tDDR2_CLK)): Read to Write from same or different bank
HI = RHC + (3 × tDDR2_CLK): Read to Read from same bank
HI = RHC + Max(IC, (3 × tDDR2_CLK)): Read to Read from different bank
IC = (number of idle cycles specified in AMICTLx register) × tDDR2_CLK
H = (number of hold cycles specified in AMICTLx register) × tDDR2_CLK
1 Data delay/setup: System must meet tDAD, tDRLD, or tSDS.
2 The falling edge of AMI_MSx, is referenced.
3 Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
4 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 58 for the calculation of hold times given capacitive and dc loads.
5 AMI_ACK delay/setup: User must meet t
DAAK, or tDSAK, for deassertion of AMI_ACK (low).
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