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參數(shù)資料
型號： ADSP-21469KBCZ-4
廠商： Analog Devices Inc
文件頁數(shù)： 32/72頁
文件大?。?/td> 0K
描述： IC DSP 32/40BIT 450MHZ 324BGA
產(chǎn)品變化通告： Pin Function Change 08/Mar/2012
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART
時(shí)鐘速率： 450MHz
非易失內(nèi)存： 外部
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.10V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 324-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 324-CSPBGA
包裝： 托盤
Rev. 0
|
Page 38 of 72
|
June 2010
ADSP-21469
Serial Ports
In slave transmitter mode and master receiver mode the maxi-
mum serial port frequency is fPCLK/8. To determine whether
communication is possible between two devices at clock speed
n, the following specifications must be confirmed: 1) frame sync
delay and frame sync setup and hold, 2) data delay and data
setup and hold, and 3) serial clock (SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins. In Figure 24 either the rising edge
or the falling edge of SCLK (external or internal) can be used as
the active sampling edge.
Table 34. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
2.5
ns
tHFSE
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
2.5
ns
tSDRE
1
Receive Data Setup Before Receive SCLK
1.9
ns
tHDRE
1
Receive Data Hold After SCLK
2.5
ns
tSCLKW
SCLK Width
(tPCLK × 4) ÷ 2 – 0.5
ns
tSCLK
SCLK Period
tPCLK × 4
ns
Switching Characteristics
tDFSE
2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
10.25
ns
tHOFSE
2
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
2
ns
tDDTE
2
Transmit Data Delay After Transmit SCLK
8.5
ns
tHDTE
2
Transmit Data Hold After Transmit SCLK
2
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 35. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
7
ns
tHFSI
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
2.5
ns
tSDRI
1
Receive Data Setup Before SCLK
7
ns
tHDRI
1
Receive Data Hold After SCLK
2.5
ns
Switching Characteristics
tDFSI
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
4
ns
tHOFSI
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0
ns
tDFSIR
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
9.75
ns
tHOFSIR
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)
–1.0
ns
tDDTI
2
Transmit Data Delay After SCLK
3.25
ns
tHDTI
2
Transmit Data Hold After SCLK
–1.25
ns
tSCLKIW
Transmit or Receive SCLK Width
2 × tPCLK – 1.5
2 × tPCLK + 1.5
ns
1 Referenced to the sample edge.
2 Referenced to drive edge.
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