- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19467 > ADSP-21469KBCZ-4 (Analog Devices Inc)IC DSP 32/40BIT 450MHZ 324BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ADSP-21469KBCZ-4 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 32/40BIT 450MHZ 324BGA |
| 產(chǎn)品變化通告： | Pin Function Change 08/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART |
| 時(shí)鐘速率： | 450MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 324-CSPBGA |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)
ADSP-21469
Rev. 0
|
Page 13 of 72
|
June 2010
DDR2_ADDR15–0
O/T
High-Z/driven
low
DDR2 Address. DDR2 address pins.
DDR2_BA2-0
O/T
High-Z/driven
low
DDR2 Bank Address Input. Defines which internal bank an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied to. BA2–0define which mode registers,
including MR, EMR, EMR(2), and EMR(3) are loaded during the LOAD MODE REGISTER
command.
DDR2_CAS
O/T
High-Z/driven
high
DDR2 Column Address Strobe. Connect to DDR2_CAS pin; in conjunction with
other DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2_CKE
O/T
High-Z/driven
low
DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2 CKE
signal.
DDR2_CS3-0
O/T
High-Z/driven
high
DDR2 Chip Select. All commands are masked when DDR2_CS3-0 is driven high.
DDR2_CS3-0 are decoded memory address lines. Each DDR2_CS3-0 line selects the
corresponding external bank.
DDR2_DATA15-0
I/O/T
High-Z
DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.
DDR2_DM1-0
O/T
High-Z/driven
high
DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled on
both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA 7–0 and
DM1 corresponds to DDR2_DATA15–8.
DDR2_DQS1-0
I/O/T (Differential)
High-Z
Data Strobe. Output with Write Data. Input with Read Data. DQS0 corresponds to
DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8. Based on software
control via the DDR2CTL3 register, this pin can be single-ended or differential.
DDR2_RAS
O/T
High-Z/driven
high
DDR2 Row Address Strobe. Connect to DDR2_RAS pin; in conjunction with other
DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2_WE
O/T
High-Z/driven
high
DDR2 Write Enable. Connect to DDR2_WE pin; in conjunction with other DDR2
command pins, defines the operation for the DDR2 to perform.
DDR2_CLK0,
DDR2_CLK1,
DDR2_CLK1
O/T (Differential)
High-Z/driven
low
DDR2 Memory Clocks. Two differential outputs available via software control
(DDR2CTL0 register). Free running, minimum frequency not guaranteed during reset.
DDR2_ODT
O/T
High-Z/driven
low
DDR2 On Die Termination. ODT pin when driven high (along with other require-
ments) enables the DDR2 termination resistances. ODT is enabled/disabled
regardless of read or write commands.
Table 9. Pin Descriptions (Continued)
Name
Type
State During/
After Reset
Description
The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k
–63 k. The range
of an ipd resistor can be between 31 k
–85 k.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAJB105M035ANJ | CAP TANT 1UF 35V 20% 1210 |
| YNV12T05-G | CONVERTER DC-DC 12V 5A SIP |
| VE-2W1-CY-F3 | CONVERTER MOD DC/DC 12V 50W |
| ADSP-21469KBCZ-3 | IC DSP 32/40BIT 400MHZ 324BGA |
| DS1620S+ | IC THERMOMETER/STAT DIG 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP21469KBCZENG | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBCZ-ENG | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBCZ-X | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBZ-EN | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBZ-ENG | 制造商:Analog Devices 功能描述:DSP FLOATING PT 32-BIT/40-BIT 450MHZ 450MIPS - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。