- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19467 > ADSP-21469KBCZ-4 (Analog Devices Inc)IC DSP 32/40BIT 450MHZ 324BGA PDF資料下載
參數(shù)資料
| 型號： | ADSP-21469KBCZ-4 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 54/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 32/40BIT 450MHZ 324BGA |
| 產(chǎn)品變化通告： | Pin Function Change 08/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART |
| 時(shí)鐘速率： | 450MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 324-CSPBGA |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當(dāng)前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
Rev. 0
|
Page 58 of 72
|
June 2010
ADSP-21469
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 19 on Page 25 through Table 54 on Page 57. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 44.
Timing is measured on signals when they cross the VMEAS level
as described in Figure 45. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches VMEAS and
the point that the second signal reaches VMEAS. The value of
VMEAS is 1.5 V for non-DDR pins and 0.9 V for DDR pins.
OUTPUT DRIVE CURRENTS
output drivers of the ADSP-21469, and Table 55 shows the pins
associated with each driver. The curves represent the current
drive capability of the output drivers as a function of output
voltage.
Figure 44. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 45. Voltage Reference Levels for AC Measurements
T1
ZO = 50
: (impedance)
TD = 4.04
r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
:
0.5pF
70
:
400
:
45
:
4pF
NOTES:
THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
:
INPUT
OR
OUTPUT
V
MEAS
V
MEAS
Table 55. Driver Types
Driver Type Associated Pins
A
LACK1–0, LDAT0[7:0], LDAT1[7:0], MLBCLK, MLBDAT,
MLBDO, MLBSIG, MLBSO, AMI_ACK,
AMI_ADDR23–0, AMI_DATA7–0, AMI_MS1–0,
AMI_RD, AMI_WR, DAI_P, DPI_P, EMU, FLAG3–0,
RESETOUT, TDO
BLCLK1–0
C
DDR2_ADDR15–0, DDR2_BA2–0, DDR2_CAS,
DDR2_CKE, DDR2_CS3–0, DDR2_DATA15–0,
DDR2_DM1–0, DDR2_ODT, DDR2_RAS, DDR2_WE
D (TRUE)
DDR2_CLK1–0, DDR2_DQS1–0
D (COMP)
DDR2_CLK1–0, DDR2_DQS1–0
Figure 46. Output Buffer Characteristics (Worst-Case Non-DDR2)
SWEEP (V
DDEXT) VOLTAGE (V)
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
0
100
200
SOURCE/SINK
(V
DDEXT
)CURRENT
(mA)
150
50
-100
-200
-150
-50
V
OH 3.13 V, 125 °C
V
OL 3.13 V, 125 °C
TYPE A
TYPE B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAJB105M035ANJ | CAP TANT 1UF 35V 20% 1210 |
| YNV12T05-G | CONVERTER DC-DC 12V 5A SIP |
| VE-2W1-CY-F3 | CONVERTER MOD DC/DC 12V 50W |
| ADSP-21469KBCZ-3 | IC DSP 32/40BIT 400MHZ 324BGA |
| DS1620S+ | IC THERMOMETER/STAT DIG 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP21469KBCZENG | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBCZ-ENG | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBCZ-X | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBZ-EN | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBZ-ENG | 制造商:Analog Devices 功能描述:DSP FLOATING PT 32-BIT/40-BIT 450MHZ 450MIPS - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。