參數(shù)資料
型號: ADSP-21469KBCZ-4
廠商: Analog Devices Inc
文件頁數(shù): 46/72頁
文件大?。?/td> 0K
描述: IC DSP 32/40BIT 450MHZ 324BGA
產(chǎn)品變化通告: Pin Function Change 08/Mar/2012
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI,EBI/EMI,I²C,SCI,SPI,SSP,UART/USART
時鐘速率: 450MHz
非易失內(nèi)存: 外部
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 324-BGA,CSPBGA
供應商設備封裝: 324-CSPBGA
包裝: 托盤
Rev. 0
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Page 50 of 72
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June 2010
ADSP-21469
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 47. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 47. S/PDIF Transmitter Input Data Timing
Parameter
Min
Max
Unit
Timing Requirements
tSISFS
1
Frame Sync Setup Before Serial Clock Rising Edge
3
ns
tSIHFS
1
Frame Sync Hold After Serial Clock Rising Edge
3
ns
tSISD
1
Data Setup Before Serial Clock Rising Edge
3
ns
tSIHD
1
Data Hold After Serial Clock Rising Edge
3
ns
tSITXCLKW
Transmit Clock Width
9
ns
tSITXCLK
Transmit Clock Period
20
ns
tSISCLKW
Clock Width
36
ns
tSISCLK
Clock Period
80
ns
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can
be either CLKIN or any of the DAI pins.
Figure 36. S/PDIF Transmitter Input Timing
SAMPLE EDGE
DAI_P20–1
(TxCLK)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
tSITXCLKW
tSITXCLK
tSISCLKW
tSISCLK
tSISFS
tSIHFS
tSISD
tSIHD
Table 48. Oversampling Clock (HFCLK) Switching Characteristics
Parameter
Max
Unit
HFCLK Frequency for HFCLK = 384 × Frame Sync
Oversampling Ratio × Frame Sync <= 1/tSIHFCLK
MHz
HFCLK Frequency for HFCLK = 256 × Frame Sync
49.2
MHz
Frame Rate (Fs)
192.0
kHz
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