參數(shù)資料
型號: ADSP-21469KBCZ-4
廠商: Analog Devices Inc
文件頁數(shù): 50/72頁
文件大?。?/td> 0K
描述: IC DSP 32/40BIT 450MHZ 324BGA
產(chǎn)品變化通告: Pin Function Change 08/Mar/2012
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI,EBI/EMI,I²C,SCI,SPI,SSP,UART/USART
時鐘速率: 450MHz
非易失內(nèi)存: 外部
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 324-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 324-CSPBGA
包裝: 托盤
Rev. 0
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Page 54 of 72
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June 2010
ADSP-21469
Media Local Bus
All the numbers given are applicable for all speed modes
(1024 Fs, 512 Fs, and 256 Fs for 3-pin; 512 Fs and 256 Fs for 5-
pin) unless otherwise specified. Please refer to MediaLB specifi-
cation document rev 3.0 for more details.
Table 52. MLB Interface, 3-Pin Specifications
Parameter
Min
Typ
Max
Unit
3-Pin Characteristics
tMLBCLK
MLB Clock Period
1024 Fs
512 Fs
256 Fs
20.3
40
81
ns
tMCKL
MLBCLK Low Time
1024 Fs
512 Fs
256 Fs
6.1
14
30
ns
tMCKH
MLBCLK High Time
1024 Fs
512 Fs
256 Fs
9.3
14
30
ns
tMCKR
MLBCLK Rise Time (VIL to VIH)
1024 Fs
512 Fs/256 Fs
1
3
ns
tMCKF
MLBCLK Fall Time (VIH to VIL)
1024 Fs
512 Fs/256 Fs
1
3
ns
tMPWV
1
MLBCLK Pulse Width Variation
1024 Fs
512 Fs/256 Fs
0.7
2.0
ns p-p
tDSMCF
DAT/SIG Input Setup Time
1
ns
tDHMCF
DAT/SIG Input Hold Time
1
ns
tMCFDZ
DAT/SIG Output Time to Three-state
0
15
ns
tMCDRV
DAT/SIG Output Data Delay From MLBCLK Rising Edge
8
ns
tMDZH
2
Bus Hold Time
1024 Fs
512 Fs/256 Fs
2
4
ns
CMLB
DAT/SIG Pin Load
1024 Fs
512 Fs/256 Fs
40
60
pf
1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in nanoseconds peak-to-peak (ns p-p).
2 The board must be designed to ensure that the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be
minimized while meeting the maximum capacitive load listed.
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