參數(shù)資料
型號: ADSP-21469KBCZ-4
廠商: Analog Devices Inc
文件頁數(shù): 38/72頁
文件大?。?/td> 0K
描述: IC DSP 32/40BIT 450MHZ 324BGA
產(chǎn)品變化通告: Pin Function Change 08/Mar/2012
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI,EBI/EMI,I²C,SCI,SPI,SSP,UART/USART
時鐘速率: 450MHz
非易失內(nèi)存: 外部
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 324-BGA,CSPBGA
供應商設備封裝: 324-CSPBGA
包裝: 托盤
ADSP-21469
Rev. 0
|
Page 43 of 72
|
June 2010
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 39. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 39. Input Data Port (IDP)
Parameter
Min
Max
Unit
Timing Requirements
tSISFS
1
Frame Sync Setup Before Serial Clock Rising Edge
3.8
ns
tSIHFS
1
Frame Sync Hold After Serial Clock Rising Edge
2.5
ns
tSISD
1
Data Setup Before Serial Clock Rising Edge
2.5
ns
tSIHD
1
Data Hold After Serial Clock Rising Edge
2.5
ns
tIDPCLKW
Clock Width
(tPCLK × 4) ÷ 2 – 1
ns
tIDPCLK
Clock Period
tPCLK × 4
ns
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can
be either CLKIN or any of the DAI pins.
Figure 28. IDP Master Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
tIPDCLK
tIPDCLKW
tSISFS
tSIHFS
tSIHD
tSISD
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