參數(shù)資料
型號： ADSP-21469KBCZ-4
廠商： Analog Devices Inc
文件頁數(shù)： 58/72頁
文件大小： 0K
描述： IC DSP 32/40BIT 450MHZ 324BGA
產(chǎn)品變化通告： Pin Function Change 08/Mar/2012
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點
接口： DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART
時鐘速率： 450MHz
非易失內(nèi)存： 外部
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.10V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 324-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 324-CSPBGA
包裝： 托盤
ADSP-21469
Rev. 0
|
Page 61 of 72
|
June 2010
THERMAL CHARACTERISTICS
The ADSP-21469 processor is rated for performance over the
temperature range specified in Operating Conditions on
Table 56 airflow measurements comply with JEDEC standards
JESD51-2 and JESD51-6, and the junction-to-board measure-
ment complies with JESD51-8. Test board design complies with
JEDEC standards JESD51-7 (CSP_BGA). The junction-to-case
measurement complies with MIL- STD-883. All measurements
use a 2S2P JEDEC test board.
To determine the junction temperature of the device while on
the application PCB use:
TJ = junction temperature (°C)
where:
TCASE = case temperature (°C) measured at the top center of the
package
JT = junction-to-top (of package) characterization parameter
is the typical value from Table 56.
PD = power dissipation
Values of JA are provided for package comparison and PCB
design considerations. JA can be used for a first order approxi-
mation of TJ by the equation:
where:
TA = ambient temperature °C
Values of JC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Figure 55. Typical Output Rise/Fall Delay DDR Pad D
(VDD_EXT = Min)
Figure 56. Typical Output Rise/Fall Delay DDR Pad C
(VDD_EXT = Max)
LOAD CAPACITANCE (pF)
2.4
0
2.6
1.8
1.6
1.4
2.8
RISE
AND
FALL
DELAY
(ns)
25
20
535
10
15
30
2.2
2.0
3.0
TYPE D HALF DRIVE TRUE (FALL)
TYPE D HALF DRIVE COMP (FALL)
y = 0.0123x + 2.3194
TYPE D HALF DRIVE TRUE (RISE)
y = 0.0077x + 2.2912
TYPE D HALF DRIVE COMP (RISE)
y = 0.0077x + 2.2398
TYPE D FULL DRIVE COMP (RISE)
y = 0.0022x + 2.1499
TYPE D FULL DRIVE TRUE (RISE & FALL)
TYPE D FULL DRIVE COMP (FALL )
y = 0.0022x + 2.2027
LOAD CAPACITANCE (pF)
0
RISE
AND
FALL
DELAY
(ns)
25
20
535
10
15
30
TYPE C HALF DRIVE (FALL)
y = 0.0046x + 1.0577
TYPE C HALF DRIVE (RISE)
y = 0.0032x + 1.0622
TYPE C FULL DRIVE (RISE & FALL)
y = 0.0007x + 0.9841
1.1
1.2
0.8
0.7
1.3
1.0
0.9
1.4
Figure 57. Typical Output Rise/Fall Delay DDR Pad D
(VDD_EXT = Max)
LOAD CAPACITANCE (pF)
1.3
0
1.4
1.0
0.9
0.8
RISE
AND
FALL
DELAY
(ns)
25
20
535
10
15
30
1.2
1.1
TYPE D HALF DRIVE TRUE (FALL)
TYPE D HALF DRIVE COMP (FALL)
y = 0.0047x + 1.1884
TYPE D HALF DRIVE TRUE (RISE)
y = 0.003x + 1.1758
TYPE D HALF DRIVE COMP (RISE)
y = 0.0031x + 1.1599
TYPE D FULL DRIVE COMP (RISE)
y = 0.0007x + 1.0964
TYPE D FULL DRIVE TRUE (RISE & FALL)
TYPE D FULL DRIVE COMP (FALL)
y = 0.0008x + 1.1074
TJ
TCASE
JT
PD
+
=
TJ
TA
JA
PD
+
=
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